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Attempt to run GL sims
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kareefardi committed Apr 17, 2024
1 parent 5192ce5 commit 3526de2
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22 changes: 22 additions & 0 deletions .github/actions/setup-openlane-nix/action.yaml
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name: 'Setup OpenLane'
description: 'Install Nix and Setup OpenLane cachix'
runs:
using: "composite"
runs-on: ubuntu-latest
steps:
- name: Maximize build space
uses: easimon/maximize-build-space@master
with:
remove-dotnet: "true"
remove-android: "true"
remove-haskell: "true"
remove-codeql: "true"
remove-docker-images: "true"
root-reserve-mb: 20480

- uses: actions/checkout@v3
- uses: DeterminateSystems/nix-installer-action@main
with:
extra-conf: |
extra-substituters = https://openlane.cachix.org
extra-trusted-public-keys = openlane.cachix.org-1:qqdwh+QMNGmZAuyeQJTH9ErW57OWSvdtuwfBKdS254E=
3 changes: 3 additions & 0 deletions .github/workflows/run_IP.yaml
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Expand Up @@ -42,13 +42,16 @@ jobs:
- name: Copy EF_UVM ot verify/uvm-python (workaround)
shell: bash
run: cp -r $(pwd) /home/runner/work/${{ inputs.name }}/verify/uvm-python/
- name: Setup OpenLane
uses: ./.github/actions/setup-openlane-nix/action.yaml
- name: Run Test
shell: bash
working-directory: /home/runner/work/${{ inputs.name }}/verify/uvm-python
run: |
for test in ${{ matrix.tests.test }}; do
echo "Running Test $test"
make run_$test
make run_gl_$test
done
- name: Tar Test Logs
shell: bash
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3 changes: 1 addition & 2 deletions Makefile.test
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Expand Up @@ -131,9 +131,8 @@ generate_gl:
@if [ -z "$(SKIP_SYNTHESIS)" ]; then \
if [ ! -d "$(OPENLANE_RUN)/final" ]; then \
echo "Generating netlist with Yosys"; \
volare enable bdc9412b3e468c102d01b7cf6337be06ec6e9c9a; \
mkdir -p $(OPENLANE_RUN); \
cd $(GRANDPARENT_DIR) && openlane --dockerized --docker-no-tty --save-views-to hdl/gl/synthesis --log-level WARNING -c DESIGN_NAME=$(DESIGN_NAME) -c VERILOG_FILES="$(PRE_SYS_FILES)" --force-run-dir $(OPENLANE_RUN) $(UVM_PY_DIR)/EF_UVM/openlane_synthesis.json; \
cd $(GRANDPARENT_DIR) && nix run github:efabless/openlane2 --save-views-to hdl/gl/synthesis --log-level WARNING -c DESIGN_NAME=$(DESIGN_NAME) -c VERILOG_FILES="$(PRE_SYS_FILES)" --force-run-dir $(OPENLANE_RUN) $(UVM_PY_DIR)/EF_UVM/openlane_synthesis.json; \
fi; \
else \
echo "Skipping synthesis because SKIP_SYNTHESIS is defined"; \
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