consider preadyout for apb monitor and driver

efabless · Oct 1, 2024 · 13c8338 · 13c8338
1 parent 2cbae20
commit 13c8338
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Showing 2 changed files with 16 additions and 3 deletions.
diff --git a/bus_env/bus_agent/bus_apb_driver.py b/bus_env/bus_agent/bus_apb_driver.py
@@ -63,7 +63,8 @@ async def read(self, addr):
         self.vif.PSEL.value = 1
         await self.drive_delay()
         self.vif.PENABLE.value = 1
-        await self.drive_delay()
+        await self.wait_ready()
+        # await self.drive_delay()
         try:
             data = self.vif.PRDATA.value.integer
         except TypeError or ValueError:
@@ -79,13 +80,16 @@ async def write(self, addr, data):
         self.vif.PSEL.value = 1
         await self.drive_delay()
         self.vif.PENABLE.value = 1
-        await self.drive_delay()
+        await self.wait_ready()
+        # await self.drive_delay()
         self.end_of_trans()
         uvm_info(self.tag, "Finished APB write to addr " + hex(addr), UVM_HIGH)
 
     def end_of_trans(self):
         self.vif.PSEL.value = 0
         self.vif.PENABLE.value = 0
 
-
+    async def wait_ready(self):
+        while self.vif.PREADY == 0:
+            await self.drive_delay()
 uvm_component_utils(bus_apb_driver)
diff --git a/bus_env/bus_agent/bus_apb_monitor.py b/bus_env/bus_agent/bus_apb_monitor.py
@@ -12,6 +12,7 @@
 class bus_apb_monitor(bus_base_monitor):
     def __init__(self, name="bus_apb_monitor", parent=None):
         super().__init__(name, parent)
+        self.counter = 0
 
     async def run_phase(self, phase):
         await cocotb.start(self.watch_reset())
@@ -34,6 +35,7 @@ async def run_phase(self, phase):
                     self.tag,
                     f"APB protocol violation: SETUP cycle not followed by ENABLE cycle PENABLE={self.vif.PENABLE.value.binstr}",
                 )
+            await self.wait_ready()
             if tr.kind == bus_item.WRITE:
                 tr.data = self.vif.PWDATA.value.integer
             else:
@@ -46,6 +48,9 @@ async def run_phase(self, phase):
                     )
                     tr.data = self.vif.PRDATA.value.binstr
             self.monitor_port.write(tr)
+            self.counter += 1
+            # if self.counter > 40:
+            #     uvm_fatal(self.tag, "sampled too many transactions")
             # update reg value #TODO: move this to the ref_model later
             # self.regs.write_reg_value(tr.addr, tr.data)
             uvm_info(
@@ -68,5 +73,9 @@ async def sample_delay(self):
         await RisingEdge(self.vif.CLK)
         # await Timer(1, "NS")
 
+    async def wait_ready(self):
+        while self.vif.PREADY == 0:
+            await self.sample_delay()
+
 
 uvm_component_utils(bus_apb_monitor)