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Uvm #2

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merged 3 commits into from
May 2, 2024
Merged

Uvm #2

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03510a7
regenerate the wrappers
M0stafaRady May 1, 2024
114876c
Fixes for AHBL
M0stafaRady May 1, 2024
3fd5f46
add wait for config phase to make sure cpa and cpo would be read afte…
M0stafaRady May 2, 2024
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10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@

module EF_SPI_AHBL #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
input wire HCLK,
input wire HRESETn,
Expand Down Expand Up @@ -127,7 +127,7 @@ module EF_SPI_AHBL #(
localparam IC_REG_OFFSET = 16'd3852;

wire clk = HCLK;
wire resetb = HRESETn;
wire rst_n = HRESETn;


reg last_HSEL, last_HWRITE; reg [31:0] last_HADDR; reg [1:0] last_HTRANS;
Expand All @@ -145,7 +145,7 @@ module EF_SPI_AHBL #(

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -215,10 +215,10 @@ module EF_SPI_AHBL #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_AHBL.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

module EF_SPI_AHBL #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
`AHBL_SLAVE_PORTS,
input [1-1:0] dout,
Expand All @@ -48,14 +48,14 @@ module EF_SPI_AHBL #(
localparam IC_REG_OFFSET = `AHBL_AW'd3852;

wire clk = HCLK;
wire resetb = HRESETn;
wire rst_n = HRESETn;


`AHBL_CTRL_SIGNALS

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -110,10 +110,10 @@ module EF_SPI_AHBL #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -85,7 +85,7 @@

module EF_SPI_APB #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
input wire PCLK,
input wire PRESETn,
Expand Down Expand Up @@ -115,7 +115,7 @@ module EF_SPI_APB #(
localparam IC_REG_OFFSET = 16'd3852;

wire clk = PCLK;
wire resetb = PRESETn;
wire rst_n = PRESETn;


wire apb_valid = PSEL & PENABLE;
Expand All @@ -124,7 +124,7 @@ module EF_SPI_APB #(

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -195,10 +195,10 @@ module EF_SPI_APB #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_APB.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

module EF_SPI_APB #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
`APB_SLAVE_PORTS,
input [1-1:0] dout,
Expand All @@ -48,14 +48,14 @@ module EF_SPI_APB #(
localparam IC_REG_OFFSET = `APB_AW'd3852;

wire clk = PCLK;
wire resetb = PRESETn;
wire rst_n = PRESETn;


`APB_CTRL_SIGNALS

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -110,10 +110,10 @@ module EF_SPI_APB #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@

module EF_SPI_WB #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
input wire ext_clk,
input wire clk_i,
Expand Down Expand Up @@ -109,7 +109,7 @@ module EF_SPI_WB #(
localparam IC_REG_OFFSET = 16'd3852;

wire clk = clk_i;
wire resetb = (~rst_i);
wire rst_n = (~rst_i);


wire wb_valid = cyc_i & stb_i;
Expand All @@ -119,7 +119,7 @@ module EF_SPI_WB #(

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -178,10 +178,10 @@ module EF_SPI_WB #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
10 changes: 5 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_WB.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

module EF_SPI_WB #(
parameter
CLK_DIVIDER_WIDTH = 8
CDW = 8
) (
`WB_SLAVE_PORTS,
input [1-1:0] dout,
Expand All @@ -48,14 +48,14 @@ module EF_SPI_WB #(
localparam IC_REG_OFFSET = `WB_AW'd3852;

wire clk = clk_i;
wire resetb = (~rst_i);
wire rst_n = (~rst_i);


`WB_CTRL_SIGNALS

wire [1-1:0] CPOL;
wire [1-1:0] CPHA;
wire [CLK_DIVIDER_WIDTH-1:0] clk_divider;
wire [CDW-1:0] clk_divider;
wire [1-1:0] go;
wire [8-1:0] datai;
wire [8-1:0] datao;
Expand Down Expand Up @@ -110,10 +110,10 @@ module EF_SPI_WB #(
assign IRQ = |MIS_REG;

EF_SPI #(
.CLK_DIVIDER_WIDTH(CLK_DIVIDER_WIDTH)
.CDW(CDW)
) instance_to_wrap (
.clk(clk),
.resetb(resetb),
.rst_n(rst_n),
.CPOL(CPOL),
.CPHA(CPHA),
.clk_divider(clk_divider),
Expand Down
2 changes: 1 addition & 1 deletion verify/uvm-python/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ MODULE ?= top_module
AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
WB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v
HDL_FILES ?= $(PWD)/../../hdl/rtl/spi_master.v
HDL_FILES ?= $(PWD)/../../hdl/rtl/spi_master.v $(PWD)/../../hdl/rtl/EF_SPI.v
VERILOG_SOURCES ?= $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
RTL_MACROS += ""
BUS_TYPE ?= APB
Expand Down
6 changes: 2 additions & 4 deletions verify/uvm-python/spi_ref_model/spi_ref_model.py
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Original file line number Diff line number Diff line change
Expand Up @@ -81,13 +81,11 @@ def write_bus(self, tr):
# TODO: write logic needed when read transaction is received
# For example, to read the same resgiter uncomment the following lines
data = self.regs.read_reg_value(tr.addr)
td = tr.do_clone()
if tr.addr == self.regs.reg_name_to_address["STATUS"]:
pass # don't change the data as the status register isnt calculated in the ref model for now
else:
pass
# td.data = data
self.bus_bus_export.write(td) # this is output to the scoreboard
tr.data = data
self.bus_bus_export.write(tr) # this is output to the scoreboard
self.update_interrupt_regs()

def write_ip(self, tr):
Expand Down
2 changes: 2 additions & 0 deletions verify/uvm-python/spi_seq_lib/configure_spi_seq.py
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,8 @@ async def body(self):
reg="CFG",
data_condition=lambda data: data in [0b00, 0b01, 0b10, 0b11],
)
rsp = []
await self.get_response(rsp) # wait until writing is done


uvm_object_utils(configure_spi_seq)
25 changes: 16 additions & 9 deletions verify/uvm-python/spi_seq_lib/spi_MOSI_MISO_seq.py
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Original file line number Diff line number Diff line change
Expand Up @@ -54,17 +54,24 @@ async def body(self):
) # go
await self.send_nop()
await self.send_nop()
# wait until the response status is busy
while True:
await self.send_req(is_write=False, reg="STATUS")
# pop non needed response in the fifo
while True:
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_LOW)
if rsp.addr == self.regs.reg_name_to_address["STATUS"]:
break
if rsp.data & 0b10 == 0b0: # not busy
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b10: # busy
break
# wait until not busy
while True:
await self.send_nop()
await self.send_req(is_write=False, reg="STATUS")
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp} id {rsp.id}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b0:
break
if random.random() > 0.3: # 70% probability of reading
await self.send_req(is_write=False, reg="DATA")
Expand Down
25 changes: 15 additions & 10 deletions verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py
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Original file line number Diff line number Diff line change
Expand Up @@ -36,20 +36,25 @@ async def body(self):
is_write=True, reg="CTRL", data_condition=lambda data: data == 0b11
) # go
for _ in range(self.num_data):
# wait until the response status is busy
while True:
await self.send_req(is_write=False, reg="STATUS")
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b10: # busy
break
# wait until not busy
while True:
await self.send_nop()
await self.send_req(is_write=False, reg="STATUS")
# pop non needed response in the fifo
while True:
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
# uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"]:
break
if rsp.data & 0b10 == 0b0: # not busy
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp} id {rsp.id}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b0:
break
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)

if random.random() > 0.1: # 90% probability of reading
await self.send_req(is_write=False, reg="DATA")
Expand Down
25 changes: 16 additions & 9 deletions verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py
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Expand Up @@ -40,17 +40,24 @@ async def body(self):
await self.send_req(
is_write=True, reg="CTRL", data_condition=lambda data: data == 0b11
) # go
# wait until the response status is busy
while True:
await self.send_req(is_write=False, reg="STATUS")
# pop non needed response in the fifo
while True:
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"]:
break
if rsp.data & 0b10 == 0b0: # not busy
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b10: # busy
break
# wait until not busy
while True:
await self.send_nop()
await self.send_req(is_write=False, reg="STATUS")
rsp = []
await self.get_response(rsp)
rsp = rsp[0]
uvm_info(self.get_full_name(), f"RSP: {rsp} id {rsp.id}", UVM_MEDIUM)
if rsp.addr == self.regs.reg_name_to_address["STATUS"] and rsp.data & 0b10 == 0b0:
break

await self.send_req(
Expand Down
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