fix typo in yaml and update wrappers

efabless · May 12, 2024 · 97957ff · 97957ff
1 parent e96df9b
commit 97957ff
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Showing 9 changed files with 21 additions and 21 deletions.
diff --git a/EF_SPI.yaml b/EF_SPI.yaml
@@ -202,7 +202,7 @@ registers:
   description: Control Register.
   fields:
   - name: SS
-    bit_offset: 1
+    bit_offset: 0
     bit_width: 1
     write_port: ss
     description: Slave Select (Active High).
@@ -253,7 +253,7 @@ fifos:
   width: 8
   address_width: FAW
   register: TXDATA
-  data_port: wdata
+  data_port: datai
   control_port: wr
   flush_enable: True
   flush_port: tx_flush

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
@@ -194,7 +194,7 @@ module EF_SPI_AHBL #(
                                             CFG_REG <= HWDATA[2-1:0];
 
 	reg [0:0]	CTRL_REG;
-	assign	ss	=	CTRL_REG[1 : 1];
+	assign	ss	=	CTRL_REG[0 : 0];
 	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) CTRL_REG <= 0;
                                         else if(ahbl_we & (last_HADDR[16-1:0]==CTRL_REG_OFFSET))
                                             CTRL_REG <= HWDATA[1-1:0];
@@ -339,6 +339,6 @@ module EF_SPI_AHBL #(
 
 	assign	RXDATA_WIRE = datao;
 	assign	rd = (ahbl_re & (last_HADDR[16-1:0] == RXDATA_REG_OFFSET));
-	// assign	wdata = PWDATA; // TODO: report bug in generate script
+	assign	datai = HWDATA;
 	assign	wr = (ahbl_we & (last_HADDR[16-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_SPI_AHBL.v b/hdl/rtl/bus_wrappers/EF_SPI_AHBL.v
@@ -92,7 +92,7 @@ module EF_SPI_AHBL #(
 	`AHBL_REG(CFG_REG, 0, 2)
 
 	reg [0:0]	CTRL_REG;
-	assign	ss	=	CTRL_REG[1 : 1];
+	assign	ss	=	CTRL_REG[0 : 0];
 	`AHBL_REG(CTRL_REG, 0, 1)
 
 	reg [CDW-1:0]	PR_REG;
@@ -216,6 +216,6 @@ module EF_SPI_AHBL #(
 
 	assign	RXDATA_WIRE = datao;
 	assign	rd = (ahbl_re & (last_HADDR[`AHBL_AW-1:0] == RXDATA_REG_OFFSET));
-	// assign	wdata = PWDATA; // TODO: report bug in generate script
+	assign	datai = HWDATA;
 	assign	wr = (ahbl_we & (last_HADDR[`AHBL_AW-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
@@ -163,7 +163,7 @@ module EF_SPI_APB #(
                                             CFG_REG <= PWDATA[2-1:0];
 
 	reg [0:0]	CTRL_REG;
-	assign	ss	=	CTRL_REG[1 : 1];
+	assign	ss	=	CTRL_REG[0 : 0];
 	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) CTRL_REG <= 0;
                                         else if(apb_we & (PADDR[16-1:0]==CTRL_REG_OFFSET))
                                             CTRL_REG <= PWDATA[1-1:0];
@@ -309,6 +309,6 @@ module EF_SPI_APB #(
 
 	assign	RXDATA_WIRE = datao;
 	assign	rd = (apb_re & (PADDR[16-1:0] == RXDATA_REG_OFFSET));
-	// assign	wdata = PWDATA; // TODO: report bug in generate script
+	assign	datai = PWDATA;
 	assign	wr = (apb_we & (PADDR[16-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_SPI_APB.v b/hdl/rtl/bus_wrappers/EF_SPI_APB.v
@@ -92,7 +92,7 @@ module EF_SPI_APB #(
 	`APB_REG(CFG_REG, 0, 2)
 
 	reg [0:0]	CTRL_REG;
-	assign	ss	=	CTRL_REG[1 : 1];
+	assign	ss	=	CTRL_REG[0 : 0];
 	`APB_REG(CTRL_REG, 0, 1)
 
 	reg [CDW-1:0]	PR_REG;
@@ -216,6 +216,6 @@ module EF_SPI_APB #(
 
 	assign	RXDATA_WIRE = datao;
 	assign	rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
-	// assign	wdata = PWDATA; // TODO: report bug in generate script
+	assign	datai = PWDATA;
 	assign	wr = (apb_we & (PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v
@@ -156,7 +156,7 @@ module EF_SPI_WB #(
 	always @(posedge clk_i or posedge rst_i) if(rst_i) CFG_REG <= 0; else if(wb_we & (adr_i[16-1:0]==CFG_REG_OFFSET)) CFG_REG <= dat_i[2-1:0];
 
 	reg [0:0]	CTRL_REG;
-	assign	ss	=	CTRL_REG[1 : 1];
+	assign	ss	=	CTRL_REG[0 : 0];
 	always @(posedge clk_i or posedge rst_i) if(rst_i) CTRL_REG <= 0; else if(wb_we & (adr_i[16-1:0]==CTRL_REG_OFFSET)) CTRL_REG <= dat_i[1-1:0];
 
 	reg [CDW-1:0]	PR_REG;
@@ -289,6 +289,6 @@ module EF_SPI_WB #(
 			ack_o <= 1'b0;
 	assign	RXDATA_WIRE = datao;
 	assign	rd =  ack_o & (wb_re & (adr_i[16-1:0] == RXDATA_REG_OFFSET));
-	// assign	wdata = PWDATA; // TODO: report bug in generate script
+	assign	datai = dat_i;
 	assign	wr = ack_o & (wb_we & (adr_i[16-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/hdl/rtl/bus_wrappers/EF_SPI_WB.v b/hdl/rtl/bus_wrappers/EF_SPI_WB.v
@@ -92,7 +92,7 @@ module EF_SPI_WB #(
 	`WB_REG(CFG_REG, 0, 2)
 
 	reg [0:0]	CTRL_REG;
-	assign	ss	=	CTRL_REG[1 : 1];
+	assign	ss	=	CTRL_REG[0 : 0];
 	`WB_REG(CTRL_REG, 0, 1)
 
 	reg [CDW-1:0]	PR_REG;
@@ -221,6 +221,6 @@ module EF_SPI_WB #(
 			ack_o <= 1'b0;
 	assign	RXDATA_WIRE = datao;
 	assign	rd =  ack_o & (wb_re & (adr_i[`WB_AW-1:0] == RXDATA_REG_OFFSET));
-	// assign	wdata = PWDATA; // TODO: report bug in generate script
+	assign	datai = dat_i;
 	assign	wr = ack_o & (wb_we & (adr_i[`WB_AW-1:0] == TXDATA_REG_OFFSET));
 endmodule
diff --git a/verify/uvm-python/spi_interface/spi_if.py b/verify/uvm-python/spi_interface/spi_if.py
@@ -6,8 +6,8 @@ def __init__(self, dut):
         bus_map = {
             "SCK": "SCK",
             "SSn": "SSn",
-            "MOSI": "MSO",
-            "MISO": "MSI",
+            "MOSI": "MOSI",
+            "MISO": "MISO",
             "CLK": "CLK",
         }
         super().__init__(dut, "", bus_map)
diff --git a/verify/uvm-python/top.v b/verify/uvm-python/top.v
@@ -6,8 +6,8 @@ module top();
     wire 		irq;
     // TODO: Add any IP signals here
 
-    wire         MSI;
-    wire         MSO;
+    wire         MISO;
+    wire         MOSI;
     wire         SSn;
     wire         SCK;
     // TODO: initialize the ABP wrapper here
@@ -20,7 +20,7 @@ module top();
         wire [31:0]	PWDATA;
         wire [31:0]	PRDATA;
         wire 		PREADY;
-        EF_SPI_APB dut(.PCLK(CLK), .PRESETn(RESETn), .PADDR(PADDR), .PWRITE(PWRITE), .PSEL(PSEL), .PENABLE(PENABLE), .PWDATA(PWDATA), .PRDATA(PRDATA), .PREADY(PREADY), .mosi(MSO), .miso(MSI), .csb(SSn), .sclk(SCK), .IRQ(irq));
+        EF_SPI_APB dut(.PCLK(CLK), .PRESETn(RESETn), .PADDR(PADDR), .PWRITE(PWRITE), .PSEL(PSEL), .PENABLE(PENABLE), .PWDATA(PWDATA), .PRDATA(PRDATA), .PREADY(PREADY), .mosi(MOSI), .miso(MISO), .csb(SSn), .sclk(SCK), .IRQ(irq));
     `endif // BUS_TYPE_APB
     `ifdef BUS_TYPE_AHB
         wire [31:0]	HADDR;
@@ -31,7 +31,7 @@ module top();
         wire [31:0]	HWDATA;
         wire [31:0]	HRDATA;
         wire 		HREADY;
-        EF_SPI_AHBL dut(.HCLK(CLK), .HRESETn(RESETn), .HADDR(HADDR), .HWRITE(HWRITE), .HSEL(HSEL), .HTRANS(HTRANS), .HWDATA(HWDATA), .HRDATA(HRDATA), .HREADY(HREADY),.HREADYOUT(HREADYOUT), .mosi(MSO), .miso(MSI), .csb(SSn), .sclk(SCK), .IRQ(irq));
+        EF_SPI_AHBL dut(.HCLK(CLK), .HRESETn(RESETn), .HADDR(HADDR), .HWRITE(HWRITE), .HSEL(HSEL), .HTRANS(HTRANS), .HWDATA(HWDATA), .HRDATA(HRDATA), .HREADY(HREADY),.HREADYOUT(HREADYOUT), .mosi(MOSI), .miso(MISO), .csb(SSn), .sclk(SCK), .IRQ(irq));
     `endif // BUS_TYPE_AHB
     `ifdef BUS_TYPE_WISHBONE
         wire [31:0] adr_i;
@@ -41,7 +41,7 @@ module top();
         wire        cyc_i;
         wire        stb_i;
         reg         ack_o;
-        EF_SPI_WB dut(.clk_i(CLK), .rst_i(~RESETn), .adr_i(adr_i), .dat_i(dat_i), .dat_o(dat_o), .sel_i(sel_i), .cyc_i(cyc_i), .stb_i(stb_i), .ack_o(ack_o),.we_i(we_i), .mosi(MSO), .miso(MSI), .csb(SSn), .sclk(SCK), .IRQ(irq));
+        EF_SPI_WB dut(.clk_i(CLK), .rst_i(~RESETn), .adr_i(adr_i), .dat_i(dat_i), .dat_o(dat_o), .sel_i(sel_i), .cyc_i(cyc_i), .stb_i(stb_i), .ack_o(ack_o),.we_i(we_i), .mosi(MOSI), .miso(MISO), .csb(SSn), .sclk(SCK), .IRQ(irq));
     `endif // BUS_TYPE_WISHBONE
     // monitor inside signals
     `ifndef SKIP_WAVE_DUMP