update wrappers and docs with the latest buswrap updates

EF_SPI.yaml

@@ -5,8 +5,8 @@ info:
   repo: github.com/efabless/EF_SPI
   owner: Efabless Corp.
   license: APACHE 2.0
-  author: Mohamed Shalan
-  email: mshalan@efabless.com
+  author: Efabless Corp.
+  email: ip_admin@efabless.com
   version: v1.0.11
   date: 17-09-2024
   category: digital

README.md

@@ -4,21 +4,30 @@ SPI master controller with receive and transmit FIFOs.
 ## The wrapped IP
 
 
- APB, AHBL, and Wishbone wrappers, generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility, are provided. All wrappers provide the same programmer's interface as outlined in the following sections.
+ APB, AHBL, and Wishbone wrappers are provided. All wrappers provide the same programmer's interface as outlined in the following sections.
 
 #### Wrapped IP System Integration
 
-Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the APB wrapper:
+Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the wishbone wrapper:
 ```verilog
-EF_SPI_APB INST (
-	`TB_APB_SLAVE_CONN,
+EF_SPI_WB INST (
+	.clk_i(clk_i),
+	.rst_i(rst_i),
+	.adr_i(adr_i),
+	.dat_i(dat_i),
+	.dat_o(dat_o),
+	.sel_i(sel_i),
+	.cyc_i(cyc_i),
+	.stb_i(stb_i),
+	.ack_o(ack_o),
+	.we_i(we_i), 
+	.IRQ(irq),
 	.miso(miso),
 	.mosi(mosi),
 	.csb(csb),
 	.sclk(sclk)
 );
 ```
-> **_NOTE:_** `TB_APB_SLAVE_CONN is a convenient macro provided by [BusWrap](https://github.com/efabless/BusWrap/tree/main).
 #### Wrappers with DFT support
 Wrappers in the directory ``/hdl/rtl/bus_wrappers/DFT`` have an extra input port ``sc_testmode`` to enable the clock gate whenever the scan chain testmode is enabled.
 
@@ -95,7 +104,7 @@ SPI clock Prescaler; should have a value >= 2. SPI Clock Frequency = System Cloc
 ### STATUS Register [Offset: 0x14, mode: r]
 
 Status resgister
-<img src="https://svg.wavedrom.com/{reg:[{name:'TX_E', bits:1},{name:'TX_F', bits:1},{name:'RX_E', bits:1},{name:'RX_F', bits:1},{name:'TX_B', bits:1},{name:'RX_A', bits:1},{bits: 26}], config: {lanes: 2, hflip: true}} "/>
+<img src="https://svg.wavedrom.com/{reg:[{name:'TX_E', bits:1},{name:'TX_F', bits:1},{name:'RX_E', bits:1},{name:'RX_F', bits:1},{name:'TX_B', bits:1},{name:'RX_A', bits:1},{name:'busy', bits:1},{name:'done', bits:1},{bits: 24}], config: {lanes: 2, hflip: true}} "/>
 
 |bit|field name|width|description|
 |---|---|---|---|
@@ -105,6 +114,8 @@ Status resgister
 |3|RX_F|1|Receive FIFO is Full.|
 |4|TX_B|1|Transmit FIFO level is Below Threshold.|
 |5|RX_A|1|Receive FIFO level is Above Threshold.|
+|6|busy|1|spi busy flag.|
+|7|done|1|spi done flag.|
 
 ### RX_FIFO_LEVEL Register [Offset: 0xfe00, mode: r]
 
@@ -172,7 +183,7 @@ TX_FIFO Flush Register
 
 ### Interrupt Flags
 
-The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility. 
+The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types.
 
 Each register has a group of bits for the interrupt sources/flags.
 - `IM` [offset: 0xff00]: is used to enable/disable interrupt sources.
@@ -195,7 +206,12 @@ The following are the bit definitions for the interrupt registers:
 |4|TXB|1|Transmit FIFO level is Below Threshold.|
 |5|RXA|1|Receive FIFO level is Above Threshold.|
 ### Clock Gating
-The IP has clock gating feature, enabling the selective activation and deactivation of the clock as required through the ``GCLK`` register. This functionality is implemented through the ``ef_gating_cell``, which is part of the the common modules library, [aucohl_lib.v](https://github.com/efabless/IP_Utilities/blob/main/rtl/aucohl_lib.v). By default, the cell operates with a behavioral implementation, but when the ``SKY130`` macro is enabled, the ``sky130_fd_sc_hd__dlclkp_4`` clock gating cell is used.
+The IP has clock gating feature, enabling the selective activation and deactivation of the clock as required through the ``GCLK`` register. This functionality is implemented through the ``ef_util_gating_cell``, which is part of the the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the cell operates with a behavioral implementation, but when the ``CLKG_SKY130_HD`` macro is enabled, the ``sky130_fd_sc_hd__dlclkp_4`` clock gating cell is used.
+**Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to add the clock gating feature, you need to add ``SKY130`` macro to the ``VERILOG_DEFINES`` configuration variable. Update the YAML configuration file as follows: 
+```
+VERILOG_DEFINES:
+- SKY130
+```
 
 ### The Interface 
 
@@ -238,47 +254,16 @@ The IP has clock gating feature, enabling the selective activation and deactivat
 |tx_level|output|FAW|TX FIFO data level.|
 |ss|input|1|None|
 |enable|input|1|enable for spi master pulse generation|
-## F/W Usage Guidelines:
-1. Set the prescaler by writing to the ``PR`` register where SPI Clock Frequency = System Clock / PR. Note: should have a value >= 2.
-2. Configure clock polarity and clock phase bu setting ``cpol`` and ``cpha`` fields in the ``CFG`` register.
-3. Set the ``SSn`` field in the ``CTRL`` register
-
+|done|output|1|spi done flag.|
+|busy|output|1|spi busy flag.|
+## Firmware Drivers:
+Firmware drivers for EF_SPI can be found in the [fw](https://github.com/efabless/EF_SPI/tree/main/fw) directory. EF_SPI driver documentation  is available [here](https://github.com/efabless/EF_SPI/blob/main/fw/README.md).
+You can also find an example C application using the EF_SPI drivers [here]().
 ## Installation:
 You can either clone repo or use [IPM](https://github.com/efabless/IPM) which is an open-source IPs Package Manager
 * To clone repo:
 ```git clone https://github.com/efabless/EF_SPI```
-> **Note:** If you choose this method, you need to clone [IP_Utilities](https://github.com/efabless/IP_Utilities/tree/main) repository, as it includes required modules from the common modules library, [aucohl_lib.v](https://github.com/efabless/IP_Utilities/blob/main/rtl/aucohl_lib.v)
+> **Note:** If you choose this method, you need to clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, as it includes required modules from the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v)
 * To download via IPM , follow installation guides [here](https://github.com/efabless/IPM/blob/main/README.md) then run 
 ```ipm install EF_SPI```
-> **Note:** This method is recommended as it automatically installs [IP_Utilities](https://github.com/efabless/IP_Utilities/tree/main) as a dependency.
-### Run cocotb UVM Testbench:
-In IP directory run:
- ```shell
- cd verify/uvm-python/
- ```
- ##### To run testbench for design with APB 
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=APB
- ```
- To run a certain test:
- ```shell
- make run_<test_name> BUS_TYPE=APB
- ```
- To run all tests with a tag: 
- ```shell
- make run_all_tests TAG=<new_tag> BUS_TYPE=APB
- ```
- ##### To run testbench for design with APB
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=AHB
- ```
- To run a certain test:
- ```shell
- make run_<test_name> BUS_TYPE=AHB
- ```
- To run all tests with a tag: 
- ```shell
- make run_all_tests TAG=<new_tag> BUS_TYPE=AHB
-```
+> **Note:** This method is recommended as it automatically installs [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) as a dependency.