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revert synchoronizer over miso and fix unit level
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@M0stafaRady
M0stafaRady committed Sep 30, 2024
1 parent 359f51b commit 2231e3d
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Showing 14 changed files with 146 additions and 80 deletions.
2 changes: 1 addition & 1 deletion EF_SPI.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -140,7 +140,7 @@ external_interface:
width: 1
direction: input
description: SPI Master In Slave Out.
sync: True
sync: False
- name: mosi
port: mosi
width: 1
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26 changes: 25 additions & 1 deletion hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
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Expand Up @@ -104,6 +104,10 @@ module EF_SPI_AHBL #(
CDW = 8,
FAW = 4
) (




input wire HCLK,
input wire HRESETn,
input wire HWRITE,
Expand Down Expand Up @@ -138,7 +142,21 @@ module EF_SPI_AHBL #(
localparam MIS_REG_OFFSET = 16'hFF04;
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;
wire clk = HCLK;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(HCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = HRESETn;


Expand Down Expand Up @@ -251,6 +269,11 @@ module EF_SPI_AHBL #(
else
TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;

localparam GCLK_REG_OFFSET = 16'hFF10;
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0;
else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET))
GCLK_REG <= HWDATA[1-1:0];

reg [5:0] IM_REG;
reg [5:0] IC_REG;
reg [5:0] RIS_REG;
Expand Down Expand Up @@ -347,6 +370,7 @@ module EF_SPI_AHBL #(
(last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG :
(last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG :
(last_HADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG :
(last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;

assign HREADYOUT = 1'b1;
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24 changes: 23 additions & 1 deletion hdl/rtl/bus_wrappers/EF_SPI_AHBL.v
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,10 @@ module EF_SPI_AHBL #(
CDW = 8,
FAW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif
`AHBL_SLAVE_PORTS,
input wire [1-1:0] miso,
output wire [1-1:0] mosi,
Expand All @@ -54,7 +58,21 @@ module EF_SPI_AHBL #(
localparam MIS_REG_OFFSET = `AHBL_AW'hFF04;
localparam RIS_REG_OFFSET = `AHBL_AW'hFF08;
localparam IC_REG_OFFSET = `AHBL_AW'hFF0C;
wire clk = HCLK;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk(HCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = HRESETn;


Expand Down Expand Up @@ -133,6 +151,9 @@ module EF_SPI_AHBL #(
assign tx_flush = TX_FIFO_FLUSH_REG[0 : 0];
`AHBL_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)

localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10;
`AHBL_REG(GCLK_REG, 0, 1)

reg [5:0] IM_REG;
reg [5:0] IC_REG;
reg [5:0] RIS_REG;
Expand Down Expand Up @@ -224,6 +245,7 @@ module EF_SPI_AHBL #(
(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG :
(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG :
(last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET) ? IC_REG :
(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG :
32'hDEADBEEF;

assign HREADYOUT = 1'b1;
Expand Down
56 changes: 19 additions & 37 deletions hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -102,10 +102,10 @@ module EF_SPI_APB #(
CDW = 8,
FAW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif




input wire PCLK,
input wire PRESETn,
input wire PWRITE,
Expand Down Expand Up @@ -140,27 +140,20 @@ module EF_SPI_APB #(
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];

`ifdef FPGA
wire clk = PCLK;
`else
(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
`endif
.GCLK(clk_g),
.GATE(clk_gated_en),
.CLK(PCLK)
);

wire clk = clk_g;
`endif
reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(PCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = PRESETn;


Expand Down Expand Up @@ -310,17 +303,6 @@ module EF_SPI_APB #(

assign IRQ = |MIS_REG;

reg [0:0] _miso_reg_[1:0];
wire _miso_w_ = _miso_reg_[1];
always@(posedge PCLK or negedge PRESETn)
if(PRESETn == 0) begin
_miso_reg_[0] <= 'b0;
_miso_reg_[1] <= 'b0;
end
else begin
_miso_reg_[0] <= miso;
_miso_reg_[1] <= _miso_reg_[0];
end
EF_SPI #(
.CDW(CDW),
.FAW(FAW)
Expand Down Expand Up @@ -349,7 +331,7 @@ module EF_SPI_APB #(
.tx_level(tx_level),
.ss(ss),
.enable(enable),
.miso(_miso_w_),
.miso(miso),
.mosi(mosi),
.csb(csb),
.sclk(sclk)
Expand Down
48 changes: 15 additions & 33 deletions hdl/rtl/bus_wrappers/EF_SPI_APB.v
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Original file line number Diff line number Diff line change
Expand Up @@ -59,27 +59,20 @@ module EF_SPI_APB #(
localparam RIS_REG_OFFSET = `APB_AW'hFF08;
localparam IC_REG_OFFSET = `APB_AW'hFF0C;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];

`ifdef FPGA
wire clk = PCLK;
`else
(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
`endif
.GCLK(clk_g),
.GATE(clk_gated_en),
.CLK(PCLK)
);

wire clk = clk_g;
`endif
reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk(PCLK),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = PRESETn;


Expand Down Expand Up @@ -201,17 +194,6 @@ module EF_SPI_APB #(

assign IRQ = |MIS_REG;

reg [0:0] _miso_reg_[1:0];
wire _miso_w_ = _miso_reg_[1];
always@(posedge PCLK or negedge PRESETn)
if(PRESETn == 0) begin
_miso_reg_[0] <= 'b0;
_miso_reg_[1] <= 'b0;
end
else begin
_miso_reg_[0] <= miso;
_miso_reg_[1] <= _miso_reg_[0];
end
EF_SPI #(
.CDW(CDW),
.FAW(FAW)
Expand Down Expand Up @@ -240,7 +222,7 @@ module EF_SPI_APB #(
.tx_level(tx_level),
.ss(ss),
.enable(enable),
.miso(_miso_w_),
.miso(miso),
.mosi(mosi),
.csb(csb),
.sclk(sclk)
Expand Down
31 changes: 26 additions & 5 deletions hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,10 @@ module EF_SPI_WB #(
CDW = 8,
FAW = 4
) (




input wire ext_clk,
input wire clk_i,
input wire rst_i,
Expand All @@ -93,10 +97,10 @@ module EF_SPI_WB #(
output reg ack_o,
input wire we_i,
output wire IRQ,
input wire [1-1:0] miso,
output wire [1-1:0] mosi,
output wire [1-1:0] csb,
output wire [1-1:0] sclk
input wire [1-1:0] miso,
output wire [1-1:0] mosi,
output wire [1-1:0] csb,
output wire [1-1:0] sclk
);

localparam RXDATA_REG_OFFSET = 16'h0000;
Expand All @@ -115,7 +119,21 @@ module EF_SPI_WB #(
localparam MIS_REG_OFFSET = 16'hFF04;
localparam RIS_REG_OFFSET = 16'hFF08;
localparam IC_REG_OFFSET = 16'hFF0C;
wire clk = clk_i;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(



// USE_POWER_PINS
.clk(clk_i),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = (~rst_i);


Expand Down Expand Up @@ -197,6 +215,9 @@ module EF_SPI_WB #(
assign tx_flush = TX_FIFO_FLUSH_REG[0 : 0];
always @(posedge clk_i or posedge rst_i) if(rst_i) TX_FIFO_FLUSH_REG <= 0; else if(wb_we & (adr_i[16-1:0]==TX_FIFO_FLUSH_REG_OFFSET)) TX_FIFO_FLUSH_REG <= dat_i[1-1:0]; else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;

localparam GCLK_REG_OFFSET = 16'hFF10;
always @(posedge clk_i or posedge rst_i) if(rst_i) GCLK_REG <= 0; else if(wb_we & (adr_i[16-1:0]==GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0];

reg [5:0] IM_REG;
reg [5:0] IC_REG;
reg [5:0] RIS_REG;
Expand Down
23 changes: 22 additions & 1 deletion hdl/rtl/bus_wrappers/EF_SPI_WB.v
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,10 @@ module EF_SPI_WB #(
CDW = 8,
FAW = 4
) (
`ifdef USE_POWER_PINS
inout VPWR,
inout VGND,
`endif
`WB_SLAVE_PORTS,
input wire [1-1:0] miso,
output wire [1-1:0] mosi,
Expand All @@ -54,7 +58,21 @@ module EF_SPI_WB #(
localparam MIS_REG_OFFSET = `WB_AW'hFF04;
localparam RIS_REG_OFFSET = `WB_AW'hFF08;
localparam IC_REG_OFFSET = `WB_AW'hFF0C;
wire clk = clk_i;

reg [0:0] GCLK_REG;
wire clk_g;
wire clk_gated_en = GCLK_REG[0];
ef_gating_cell clk_gate_cell(
`ifdef USE_POWER_PINS
.vpwr(VPWR),
.vgnd(VGND),
`endif // USE_POWER_PINS
.clk(clk_i),
.clk_en(clk_gated_en),
.clk_o(clk_g)
);

wire clk = clk_g;
wire rst_n = (~rst_i);


Expand Down Expand Up @@ -133,6 +151,9 @@ module EF_SPI_WB #(
assign tx_flush = TX_FIFO_FLUSH_REG[0 : 0];
`WB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)

localparam GCLK_REG_OFFSET = `WB_AW'hFF10;
`WB_REG(GCLK_REG, 0, 1)

reg [5:0] IM_REG;
reg [5:0] IC_REG;
reg [5:0] RIS_REG;
Expand Down
3 changes: 3 additions & 0 deletions ip/.gitignore
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@@ -0,0 +1,3 @@
*
!dependencies.json
!.gitignore
7 changes: 7 additions & 0 deletions ip/dependencies.json
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@@ -0,0 +1,7 @@
{
"IP": [
{
"IP_Utilities": "v1.0.0"
}
]
}
2 changes: 1 addition & 1 deletion verify/uvm-python/Makefile
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Expand Up @@ -4,7 +4,7 @@ MODULE ?= top_module
AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
WB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v
HDL_FILES ?= $(PWD)/IP_Utilities/rtl/aucohl_lib.v $(PWD)/IP_Utilities/rtl/aucohl_rtl.vh $(PWD)/../../hdl/rtl/spi_master.v $(PWD)/../../hdl/rtl/EF_SPI.v
HDL_FILES ?= $(PWD)/../../ip/IP_Utilities/rtl/aucohl_lib.v $(PWD)/../../ip/IP_Utilities/rtl/aucohl_rtl.vh $(PWD)/../../hdl/rtl/spi_master.v $(PWD)/../../hdl/rtl/EF_SPI.v

VERILOG_SOURCES ?= $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
RTL_MACROS += ""
Expand Down
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