fix testbench and add done, busy to the status register

EF_SPI.yaml

@@ -133,6 +133,14 @@ ports:
   width: 1
   direction: input
   description: enable for spi master pulse generation
+- name: done
+  width: 1
+  direction: output
+  description: spi done flag.
+- name: busy
+  width: 1
+  direction: output
+  description: spi busy flag.
 
 external_interface:
 - name: miso
@@ -231,7 +239,7 @@ registers:
   write_port: clk_divider
   description: SPI clock Prescaler; should have a value >= 2. SPI Clock Frequency = System Clock / PR.
 - name: STATUS
-  size: 6
+  size: 8
   mode: r
   fifo: no
   offset: 20
@@ -269,6 +277,16 @@ registers:
       bit_width: 1
       read_port: rx_level_above
       description: Receive FIFO level is Above Threshold.
+    - name : busy
+      bit_offset: 6
+      bit_width: 1
+      read_port: busy
+      description: spi busy flag.
+    - name : done
+      bit_offset: 7
+      bit_width: 1
+      read_port: done
+      description: spi done flag.
 
 
 flags:

hdl/rtl/EF_SPI.v

@@ -49,8 +49,8 @@ module EF_SPI #(parameter
     output wire             tx_level_below,
     output wire [FAW-1:0]   tx_level,
 
-    //output              busy,
-    //output              done,
+    output              busy,
+    output              done,
 
     input  wire             miso,
     output wire             mosi,
@@ -61,9 +61,6 @@ module EF_SPI #(parameter
 
     localparam FDW = 8;
 
-    wire              busy;
-    wire              done;
-
     // TX Side
     wire        tx_wr       = wr;
     wire        tx_rd       = !tx_empty & !busy;

hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v

@@ -200,6 +200,8 @@ module EF_SPI_AHBL #(
 	wire [FAW-1:0]	tx_level;
 	wire [1-1:0]	ss;
 	wire [1-1:0]	enable;
+	wire [1-1:0]	done;
+	wire [1-1:0]	busy;
 
 	// Register Definitions
 	wire	[8-1:0]	RXDATA_WIRE;
@@ -227,13 +229,15 @@ module EF_SPI_AHBL #(
                                         else if(ahbl_we & (last_HADDR[16-1:0]==PR_REG_OFFSET))
                                             PR_REG <= HWDATA[CDW-1:0];
 
-	wire [6-1:0]	STATUS_WIRE;
+	wire [8-1:0]	STATUS_WIRE;
 	assign	STATUS_WIRE[0 : 0] = tx_empty;
 	assign	STATUS_WIRE[1 : 1] = tx_full;
 	assign	STATUS_WIRE[2 : 2] = rx_empty;
 	assign	STATUS_WIRE[3 : 3] = rx_full;
 	assign	STATUS_WIRE[4 : 4] = tx_level_below;
 	assign	STATUS_WIRE[5 : 5] = rx_level_above;
+	assign	STATUS_WIRE[6 : 6] = busy;
+	assign	STATUS_WIRE[7 : 7] = done;
 
 	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
@@ -347,6 +351,8 @@ module EF_SPI_AHBL #(
 		.tx_level(tx_level),
 		.ss(ss),
 		.enable(enable),
+		.done(done),
+		.busy(busy),
 		.miso(miso),
 		.mosi(mosi),
 		.csb(csb),

hdl/rtl/bus_wrappers/EF_SPI_AHBL.v

@@ -100,6 +100,8 @@ module EF_SPI_AHBL #(
 	wire [FAW-1:0]	tx_level;
 	wire [1-1:0]	ss;
 	wire [1-1:0]	enable;
+	wire [1-1:0]	done;
+	wire [1-1:0]	busy;
 
 	// Register Definitions
 	wire	[8-1:0]	RXDATA_WIRE;
@@ -121,13 +123,15 @@ module EF_SPI_AHBL #(
 	assign	clk_divider = PR_REG;
 	`AHBL_REG(PR_REG, 'h2, CDW)
 
-	wire [6-1:0]	STATUS_WIRE;
+	wire [8-1:0]	STATUS_WIRE;
 	assign	STATUS_WIRE[0 : 0] = tx_empty;
 	assign	STATUS_WIRE[1 : 1] = tx_full;
 	assign	STATUS_WIRE[2 : 2] = rx_empty;
 	assign	STATUS_WIRE[3 : 3] = rx_full;
 	assign	STATUS_WIRE[4 : 4] = tx_level_below;
 	assign	STATUS_WIRE[5 : 5] = rx_level_above;
+	assign	STATUS_WIRE[6 : 6] = busy;
+	assign	STATUS_WIRE[7 : 7] = done;
 
 	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
@@ -222,6 +226,8 @@ module EF_SPI_AHBL #(
 		.tx_level(tx_level),
 		.ss(ss),
 		.enable(enable),
+		.done(done),
+		.busy(busy),
 		.miso(miso),
 		.mosi(mosi),
 		.csb(csb),

hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v

@@ -183,6 +183,8 @@ module EF_SPI_APB #(
 	wire [FAW-1:0]	tx_level;
 	wire [1-1:0]	ss;
 	wire [1-1:0]	enable;
+	wire [1-1:0]	done;
+	wire [1-1:0]	busy;
 
 	// Register Definitions
 	wire	[8-1:0]	RXDATA_WIRE;
@@ -210,13 +212,15 @@ module EF_SPI_APB #(
                                         else if(apb_we & (PADDR[16-1:0]==PR_REG_OFFSET))
                                             PR_REG <= PWDATA[CDW-1:0];
 
-	wire [6-1:0]	STATUS_WIRE;
+	wire [8-1:0]	STATUS_WIRE;
 	assign	STATUS_WIRE[0 : 0] = tx_empty;
 	assign	STATUS_WIRE[1 : 1] = tx_full;
 	assign	STATUS_WIRE[2 : 2] = rx_empty;
 	assign	STATUS_WIRE[3 : 3] = rx_full;
 	assign	STATUS_WIRE[4 : 4] = tx_level_below;
 	assign	STATUS_WIRE[5 : 5] = rx_level_above;
+	assign	STATUS_WIRE[6 : 6] = busy;
+	assign	STATUS_WIRE[7 : 7] = done;
 
 	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
@@ -331,6 +335,8 @@ module EF_SPI_APB #(
 		.tx_level(tx_level),
 		.ss(ss),
 		.enable(enable),
+		.done(done),
+		.busy(busy),
 		.miso(miso),
 		.mosi(mosi),
 		.csb(csb),

hdl/rtl/bus_wrappers/EF_SPI_APB.v

@@ -100,6 +100,8 @@ module EF_SPI_APB #(
 	wire [FAW-1:0]	tx_level;
 	wire [1-1:0]	ss;
 	wire [1-1:0]	enable;
+	wire [1-1:0]	done;
+	wire [1-1:0]	busy;
 
 	// Register Definitions
 	wire	[8-1:0]	RXDATA_WIRE;
@@ -121,13 +123,15 @@ module EF_SPI_APB #(
 	assign	clk_divider = PR_REG;
 	`APB_REG(PR_REG, 'h2, CDW)
 
-	wire [6-1:0]	STATUS_WIRE;
+	wire [8-1:0]	STATUS_WIRE;
 	assign	STATUS_WIRE[0 : 0] = tx_empty;
 	assign	STATUS_WIRE[1 : 1] = tx_full;
 	assign	STATUS_WIRE[2 : 2] = rx_empty;
 	assign	STATUS_WIRE[3 : 3] = rx_full;
 	assign	STATUS_WIRE[4 : 4] = tx_level_below;
 	assign	STATUS_WIRE[5 : 5] = rx_level_above;
+	assign	STATUS_WIRE[6 : 6] = busy;
+	assign	STATUS_WIRE[7 : 7] = done;
 
 	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
@@ -222,6 +226,8 @@ module EF_SPI_APB #(
 		.tx_level(tx_level),
 		.ss(ss),
 		.enable(enable),
+		.done(done),
+		.busy(busy),
 		.miso(miso),
 		.mosi(mosi),
 		.csb(csb),

hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v

@@ -164,6 +164,8 @@ module EF_SPI_WB #(
 	wire [FAW-1:0]	tx_level;
 	wire [1-1:0]	ss;
 	wire [1-1:0]	enable;
+	wire [1-1:0]	done;
+	wire [1-1:0]	busy;
 
 	// Register Definitions
 	wire	[8-1:0]	RXDATA_WIRE;
@@ -185,13 +187,15 @@ module EF_SPI_WB #(
 	assign	clk_divider = PR_REG;
 	always @(posedge clk_i or posedge rst_i) if(rst_i) PR_REG <= 'h2; else if(wb_we & (adr_i[16-1:0]==PR_REG_OFFSET)) PR_REG <= dat_i[CDW-1:0];
 
-	wire [6-1:0]	STATUS_WIRE;
+	wire [8-1:0]	STATUS_WIRE;
 	assign	STATUS_WIRE[0 : 0] = tx_empty;
 	assign	STATUS_WIRE[1 : 1] = tx_full;
 	assign	STATUS_WIRE[2 : 2] = rx_empty;
 	assign	STATUS_WIRE[3 : 3] = rx_full;
 	assign	STATUS_WIRE[4 : 4] = tx_level_below;
 	assign	STATUS_WIRE[5 : 5] = rx_level_above;
+	assign	STATUS_WIRE[6 : 6] = busy;
+	assign	STATUS_WIRE[7 : 7] = done;
 
 	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
@@ -290,6 +294,8 @@ module EF_SPI_WB #(
 		.tx_level(tx_level),
 		.ss(ss),
 		.enable(enable),
+		.done(done),
+		.busy(busy),
 		.miso(miso),
 		.mosi(mosi),
 		.csb(csb),

hdl/rtl/bus_wrappers/EF_SPI_WB.v

@@ -100,6 +100,8 @@ module EF_SPI_WB #(
 	wire [FAW-1:0]	tx_level;
 	wire [1-1:0]	ss;
 	wire [1-1:0]	enable;
+	wire [1-1:0]	done;
+	wire [1-1:0]	busy;
 
 	// Register Definitions
 	wire	[8-1:0]	RXDATA_WIRE;
@@ -121,13 +123,15 @@ module EF_SPI_WB #(
 	assign	clk_divider = PR_REG;
 	`WB_REG(PR_REG, 'h2, CDW)
 
-	wire [6-1:0]	STATUS_WIRE;
+	wire [8-1:0]	STATUS_WIRE;
 	assign	STATUS_WIRE[0 : 0] = tx_empty;
 	assign	STATUS_WIRE[1 : 1] = tx_full;
 	assign	STATUS_WIRE[2 : 2] = rx_empty;
 	assign	STATUS_WIRE[3 : 3] = rx_full;
 	assign	STATUS_WIRE[4 : 4] = tx_level_below;
 	assign	STATUS_WIRE[5 : 5] = rx_level_above;
+	assign	STATUS_WIRE[6 : 6] = busy;
+	assign	STATUS_WIRE[7 : 7] = done;
 
 	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
@@ -222,6 +226,8 @@ module EF_SPI_WB #(
 		.tx_level(tx_level),
 		.ss(ss),
 		.enable(enable),
+		.done(done),
+		.busy(busy),
 		.miso(miso),
 		.mosi(mosi),
 		.csb(csb),

verify/uvm-python/spi_seq_lib/configure_spi_seq.py

@@ -20,12 +20,15 @@ async def body(self):
         # Add the sequqnce here
         # you could use method send_req to send a write or read using the register name
         # example for writing register by value > 5
+        await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1)
         await self.send_req(
             is_write=True,
             reg="CFG",
             # data_condition=lambda data: data in [0b00, 0b01, 0b10, 0b11],
             data_condition=lambda data: data in [0b00, 0b01, 0b11],
         )
+        await self.send_nop()
+        await self.send_nop()
         rsp = []
         await self.get_response(rsp)  # wait until writing is done
 

verify/uvm-python/spi_seq_lib/spi_MOSI_MISO_seq.py

@@ -36,7 +36,6 @@ def __init__(
 
     async def body(self):
         await super().body()
-        await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1)
         if not self.disable_control:
             await self.send_req(
                 is_write=True, reg="CTRL", data_condition=lambda data: data == 0b0

verify/uvm-python/spi_seq_lib/spi_base_seq.py

@@ -6,6 +6,8 @@
 from cocotb.triggers import Timer
 from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do
 import random
+from uvm.macros import uvm_component_utils, uvm_fatal, uvm_info, uvm_error, uvm_warning
+from uvm.base.uvm_object_globals import UVM_HIGH, UVM_LOW, UVM_MEDIUM
 
 
 class spi_base_seq(bus_seq_base):
@@ -16,7 +18,7 @@ def __init__(self, name="spi_base_seq"):
         super().__init__(name)
 
     async def wait_tx_fifo_empty(self):
-        # wait until tx is empty
+        # wait until tx is empty and not busy
         self.clear_response_queue()
         while True:
             rsp = []
@@ -25,33 +27,38 @@ async def wait_tx_fifo_empty(self):
             rsp = rsp[0]
             if (
                 rsp.addr == self.regs.reg_name_to_address["STATUS"]
-                and rsp.data & 0b1 == 0b1
+                and rsp.data & 0b1 == 0b1 and rsp.data & 0b1000000 == 0b0
             ):
                 break
-
+        # wait until not busy
         cycles_additional = 8 * 4
         for _ in range(cycles_additional):
             await self.send_nop()
 
     async def wait_rx_fifo_not_empty(self):
         # wait received fifo not empty
         self.clear_response_queue()
+        await self.send_req(
+            is_write=True,
+            reg="TXDATA",
+            data_condition=lambda data: data == 0,
+        )
         while True:
             rsp = []
             self.clear_response_queue()
             await self.send_req(is_write=False, reg="STATUS")
-            await self.get_response(rsp)
+            while self.response_queue.size() != 0:
+                await self.get_response(rsp)
+                uvm_info(self.get_full_name(), f"RSP: {rsp}", UVM_HIGH)
+                if rsp[0].addr == self.regs.reg_name_to_address["STATUS"]:
+                    break
             rsp = rsp[0]
             if (
                 rsp.addr == self.regs.reg_name_to_address["STATUS"]
                 and rsp.data & 0b100 == 0b0
             ):
                 break
-            await self.send_req(
-                is_write=True,
-                reg="TXDATA",
-                data_condition=lambda data: data == 0,
-            )
+
 
 
 uvm_object_utils(spi_base_seq)

verify/uvm-python/spi_seq_lib/spi_rx_dis_seq.py

@@ -32,7 +32,6 @@ async def body(self):
         # Add the sequqnce here
         # you could use method send_req to send a write or read using the register name
         # example for writing register by value > 5
-        await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1)
         await self.send_req(
             is_write=True, reg="CTRL", data_condition=lambda data: data == 0b011
         )

verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py

@@ -30,14 +30,14 @@ async def body(self):
         # Add the sequqnce here
         # you could use method send_req to send a write or read using the register name
         # example for writing register by value > 5
-        await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1)
         await self.send_req(
             is_write=True, reg="CTRL", data_condition=lambda data: data == 0b111
         )
         for _ in range(self.num_data):
             await self.wait_rx_fifo_not_empty()
             if random.random() < 0.7:  # 20% probability of reading
                 await self.send_req(is_write=False, reg="RXDATA")
+            uvm_info(self.tag, f"interation number {_}", UVM_MEDIUM)
 
         await self.send_req(
             is_write=True, reg="CTRL", data_condition=lambda data: data == 0b0

verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py

@@ -30,7 +30,6 @@ async def body(self):
         # Add the sequqnce here
         # you could use method send_req to send a write or read using the register name
         # example for writing register by value > 5
-        await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1)
         await self.send_req(
             is_write=True, reg="CTRL", data_condition=lambda data: data == 0b11
         )