A generic 8-bit General Purpose I/O (GPIO) Peripheral with the following features

• Eight bidirectional pins.
• Input synchronizers
• Input edge detectors.
• Direction control.
• Edge and Level Interrupts generation per pin.
• Wrappers for AHB-Lite, APB and WB buses.

APB, AHBL, and Wishbone wrappers are provided. All wrappers provide the same programmer's interface as outlined in the following sections.

Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the wishbone wrapper:

EF_GPIO8_WB INST (
	.clk_i(clk_i),
	.rst_i(rst_i),
	.adr_i(adr_i),
	.dat_i(dat_i),
	.dat_o(dat_o),
	.sel_i(sel_i),
	.cyc_i(cyc_i),
	.stb_i(stb_i),
	.ack_o(ack_o),
	.we_i(we_i), 
	.IRQ(irq),
	.io_in(io_in),
	.io_out(io_out),
	.io_oe(io_oe)
);

Wrappers in the directory /hdl/rtl/bus_wrappers/DFT have an extra input port sc_testmode to disable the clock gate whenever the scan chain testmode is enabled.

The following table is the result for implementing the EF_GPIO8 IP with different wrappers using Sky130 PDK and OpenLane2 flow.

Data In Register; Reading from this register returns the pins status (8 pins); one bit per pin

Data Out Register; Writing to this register change the status of the port pins (8 pins); one bit per pin

Direction Register; One bit per pin 1: output, 0: input

Gated clock enable register

The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types.

Each register has a group of bits for the interrupt sources/flags.

• IM [offset: 0xff00]: is used to enable/disable interrupt sources.

• RIS [offset: 0xff08]: has the current interrupt status (interrupt flags) whether they are enabled or disabled.

• MIS [offset: 0xff04]: is the result of masking (ANDing) RIS by IM.

• IC [offset: 0xff0c]: is used to clear an interrupt flag.

The following are the bit definitions for the interrupt registers:

The IP includes a clock gating feature that allows selective activation and deactivation of the clock using the GCLK register. This capability is implemented through the ef_util_gating_cell module, which is part of the common modules library, ef_util_lib.v. By default, the clock gating is disabled. To enable behavioral implmentation clock gating, only for simulation purposes, you should define the CLKG_GENERIC macro. Alternatively, define the CLKG_SKY130_HD macro if you wish to use the SKY130 HD library clock gating cell, sky130_fd_sc_hd__dlclkp_4.

Note: If you choose the OpenLane2 flow for implementation and would like to enable the clock gating feature, you need to add CLKG_SKY130_HD macro to the VERILOG_DEFINES configuration variable. Update OpenLane2 YAML configuration file as follows:

VERILOG_DEFINES:
- CLKG_SKY130_HD

Firmware drivers for EF_GPIO8 can be found in the fw directory. EF_GPIO8 driver documentation is available here. You can also find an example C application using the EF_GPIO8 drivers here.

You can install the IP either by cloning this repository or by using IPM.

• [Optional] If you do not have IPM installed, follow the installation guide here
• After installing IPM, execute the following command ipm install EF_GPIO8.

Note: This method is recommended as it automatically installs EF_IP_UTIL as a dependency.

• Clone EF_IP_UTIL repository, which includes the required modules from the common modules library, ef_util_lib.v. git clone https://github.com/efabless/EF_IP_UTIL.git
• Clone the IP repository git clone github.com/efabless/EF_GPIO8