Various fixes after rebase

Signed-off-by: Krzysztof Boronski <[email protected]>

f4pga/__init__.py

@@ -43,25 +43,8 @@
 from f4pga.common import set_verbosity_level, sfprint
 from f4pga.argparser import setup_argparser
 from f4pga.commands import cmd_build, cmd_show_dependencies, f4pga_done
-from os import environ
-from sys import argv as sys_argv
 from pathlib import Path
 
-F4CACHEPATH = '.f4cache'
-
-install_dir = environ.get("F4PGA_INSTALL_DIR", "/usr/local")
-
-mypath = str(Path(__file__).resolve().parent)
-
-FPGA_FAM = environ.get('FPGA_FAM', 'xc7')
-
-bin_dir_path = str(Path(sys_argv[0]).resolve().parent.parent)
-share_dir_path = \
-    environ.get('F4PGA_SHARE_DIR',
-                str(Path(f'{install_dir}/{FPGA_FAM}/share/f4pga').resolve()))
-
-aux_dir_path = str(Path(mypath).joinpath('aux'))
-
 
 def platform_stages(platform_flow, r_env):
     """Iterates over all stages available in a given flow."""

f4pga/commands.py

@@ -25,10 +25,8 @@
 from colorama import Fore, Style
 from yaml import load as yaml_load, Loader as yaml_loader
 
-from f4pga.context import FPGA_FAM
+from f4pga.context import F4PGA_SHARE_DIR, FPGA_FAM, F4PGA_BIN_DIR, F4PGA_AUX_DIR, PKG_ROOT, F4CACHEPATH
 from f4pga.common import (
-    bin_dir_path,
-    share_dir_path,
     F4PGAException,
     ResolutionEnv,
     fatal,
@@ -49,9 +47,6 @@
 from f4pga.flow import Flow
 from f4pga.stage import Stage
 from f4pga.module_inspector import get_module_info
-from f4pga import mypath, F4CACHEPATH, aux_dir_path
-
-ROOT = mypath.resolve().parent
 
 
 def display_dep_info(stages: "Iterable[Stage]"):
@@ -119,9 +114,9 @@ def setup_resolution_env():
     """Sets up a ResolutionEnv with default built-ins."""
 
     r_env = ResolutionEnv({
-        "shareDir": share_dir_path,
-        "binDir": bin_dir_path,
-        "auxDir": aux_dir_path
+        "shareDir": str(F4PGA_SHARE_DIR),
+        "binDir": F4PGA_BIN_DIR,
+        "auxDir": F4PGA_AUX_DIR
     })
 
     def _noisy_warnings():
@@ -159,7 +154,7 @@ def open_project_flow_config(path: str) -> ProjectFlowConfig:
 def verify_part_stage_params(flow_cfg: FlowConfig, part: "str | None" = None):
     if part:
         platform_name = get_platform_name_for_part(part)
-        if not verify_platform_name(platform_name, str(ROOT)):
+        if not verify_platform_name(platform_name, PKG_ROOT):
             sfprint(0, f"Platform `{part}`` is unsupported.")
             return False
         if part not in flow_cfg.part():
@@ -175,7 +170,7 @@ def get_platform_name_for_part(part_name: str):
     The reason for such distinction is that plenty of chips with different names
     differ only in a type of package they use.
     """
-    with (ROOT / "part_db.yml").open("r") as rfptr:
+    with (Path(PKG_ROOT) / "part_db.yml").open("r") as rfptr:
         for key, val in yaml_load(rfptr, yaml_loader).items():
             if part_name.upper() in val:
                 return key
@@ -195,9 +190,9 @@ def make_flow_config(project_flow_cfg: ProjectFlowConfig, part_name: str) -> Flo
     r_env = setup_resolution_env()
     r_env.add_values({"part_name": part_name.lower()})
 
-    scan_modules(str(ROOT))
+    scan_modules(PKG_ROOT)
 
-    with (ROOT / "platforms.yml").open("r") as rfptr:
+    with (Path(PKG_ROOT) / "platforms.yml").open("r") as rfptr:
         platforms = yaml_load(rfptr, yaml_loader)
     if platform not in platforms:
         raise F4PGAException(message=f"Flow definition for platform <{platform}> cannot be found!")

f4pga/common.py

@@ -28,10 +28,6 @@
 from f4pga.context import F4PGA_SHARE_DIR
 
 
-bin_dir_path = str(Path(sys_argv[0]).resolve().parent.parent)
-share_dir_path = str(F4PGA_SHARE_DIR)
-
-
 class F4PGAException(Exception):
     def __init__(self, message="unknown exception"):
         self.message = message

f4pga/common_modules/generic_script_wrapper.py

@@ -72,40 +72,6 @@ def _get_param(params, name: str):
 
 
 def _parse_param_def(param_def: str):
-    if param_def[0] == "#":
-        return "positional", int(param_def[1:])
-    elif param_def[0] == "$":
-        return "environmental", param_def[1:]
-    return "named", param_def
-
-
-class InputReferences:
-    dependencies: "set[str]"
-    values: "set[str]"
-
-    def merge(self, other):
-        self.dependencies.update(other.dependencies)
-        self.values.update(other.values)
-
-    def __init__(self):
-        self.dependencies = set()
-        self.values = set()
-
-
-def _get_input_references(input: str) -> InputReferences:
-    refs = InputReferences()
-    if type(input) is not str:
-        return refs
-    for match in re_finditer("\$\{([^${}]*)\}", input):
-        match_str = match.group(1)
-        if match_str[0] != ":":
-            refs.values.add(match_str)
-            continue
-        if len(match_str) < 2:
-            raise Exception("Dependency name must be at least 1 character long")
-        refs.dependencies.add(re_match("([^\\[\\]]*)", match_str[1:]).group(1))
-    return refs
-
     if param_def[0] == '#':
         return 'positional', int(param_def[1:])
     elif param_def[0] == '$':
@@ -157,7 +123,6 @@ def map_io(self, ctx: ModuleContext):
 
     def execute(self, ctx: ModuleContext):
         cwd = ctx.r_env.resolve(self.cwd)
-
         sub_args = [ctx.r_env.resolve(self.script_path, final=True)] + self.get_args(ctx)
         if self.interpreter:
             sub_args = [ctx.r_env.resolve(self.interpreter, final=True)] + sub_args

f4pga/common_modules/place.py

@@ -45,7 +45,7 @@ def map_io(self, ctx: ModuleContext):
     def execute(self, ctx: ModuleContext):
         place_constraints = ctx.takes.place_constraints
 
-        build_dir = ctx.takes.build_dir
+        build_dir = str(Path(ctx.takes.eblif).parent)
 
         vpr_options = []
         if place_constraints:
@@ -54,17 +54,7 @@ def execute(self, ctx: ModuleContext):
         yield 'Running VPR...'
         vprargs = VprArgs(ctx.share, ctx.takes.eblif, ctx.values,
                           sdc_file=ctx.takes.sdc, vpr_extra_opts=vpr_options)
-        common_vpr(
-            "place",
-            VprArgs(
-                ctx.share,
-                ctx.takes.eblif,
-                ctx.values,
-                sdc_file=ctx.takes.sdc,
-                vpr_extra_opts=["--fix_clusters", place_constraints],
-            ),
-            cwd=build_dir,
-        )
+        common_vpr("place", vprargs, cwd=build_dir)
 
         # VPR names output on its own. If user requested another name, the
         # output file should be moved.
@@ -74,7 +64,7 @@ def execute(self, ctx: ModuleContext):
         # modules may produce some temporary files with names that differ from
         # the ones in flow configuration.
         if ctx.is_output_explicit("place"):
-            Path(default_output_name(str(place_constraints))).rename(ctx.outputs.place)
+            Path(default_output_name(str(ctx.takes.eblif))).rename(ctx.outputs.place)
 
         yield "Saving log..."
         save_vpr_log("place.log", build_dir=build_dir)

f4pga/context.py

@@ -19,6 +19,7 @@
 
 from pathlib import Path
 from os import environ
+from sys import argv as sys_argv
 
 
 FPGA_FAM = environ.get("FPGA_FAM", "xc7")
@@ -38,3 +39,13 @@
     F4PGA_INSTALL_DIR = Path(install_dir)
 
 F4PGA_SHARE_DIR = Path(environ.get("F4PGA_SHARE_DIR", F4PGA_INSTALL_DIR / FPGA_FAM / "share/f4pga"))
+
+F4CACHEPATH = '.f4cache'
+
+PKG_ROOT = str(Path(__file__).resolve().parent)
+ROOT = str(Path(PKG_ROOT).parent)
+
+FPGA_FAM = environ.get('FPGA_FAM', 'xc7')
+
+F4PGA_BIN_DIR = str(Path(sys_argv[0]).resolve().parent.parent)
+F4PGA_AUX_DIR = str(Path(PKG_ROOT).joinpath('aux'))

f4pga/flow.py

@@ -21,12 +21,12 @@
 
 from colorama import Fore, Style
 
-from f4pga.common import deep, sfprint, bin_dir_path, share_dir_path, F4PGAException, fatal
+from f4pga.common import deep, sfprint, F4PGAException, fatal
 from f4pga.cache import F4Cache
 from f4pga.flow_config import FlowConfig
 from f4pga.module_runner import ModRunCtx, module_map, module_exec
 from f4pga.stage import Stage
-from f4pga import bin_dir_path, aux_dir_path
+from f4pga.context import F4PGA_BIN_DIR, F4PGA_AUX_DIR, F4PGA_SHARE_DIR
 
 
 class Flow:
@@ -104,7 +104,7 @@ def _config_mod_runctx(
             elif config_paths.get(prod.name):
                 produces[prod.name] = config_paths[prod.name]
 
-        return ModRunCtx(share_dir_path, bin_dir_path, aux_dir_path, {"takes": takes, "produces": produces, "values": values})
+        return ModRunCtx(F4PGA_SHARE_DIR, F4PGA_BIN_DIR, F4PGA_AUX_DIR, {"takes": takes, "produces": produces, "values": values})
 
     @staticmethod
     def _cache_deps(path: str, f4cache: F4Cache):

f4pga/flow_config.py

@@ -74,7 +74,7 @@ def __init__(self, flow_def: dict, r_env: ResolutionEnv):
             self.r_env.add_values(global_vals)
 
         for stage_name, stage_def in flow_def["stages"].items():
-            self.stages[stage_name] = Stage(stage_name, stage_def)
+            self.stages[stage_name] = Stage(stage_name, stage_def, self.r_env)
 
     def stage_names(self):
         return self.stages.keys()
@@ -144,8 +144,9 @@ def __init__(self, project_config: ProjectFlowConfig, platform_def: FlowDefiniti
         self.stages = platform_def.stages
         self.part = part
 
+        raw_project_deps = project_config.get_dependencies_raw(part)
         self.dependencies_explicit = deep(lambda p: str(Path(p).resolve()))(
-            self.r_env.resolve(project_config.get_dependencies_raw(part))
+            self.r_env.resolve(raw_project_deps)
         )
 
         for stage_name, stage in platform_def.stages.items():