Remove verilog file if exists before generate it

chipsalliance · Mar 7, 2024 · 0661927 · 0661927
1 parent a4415ab
commit 0661927
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/src/main/scala/gcd/GCD.scala b/src/main/scala/gcd/GCD.scala
@@ -42,5 +42,8 @@ object GCD extends App {
       new GCD(),
       firtoolOpts = Array("-disable-all-randomization",
                           "-strip-debug-info"))
-  os.write(os.pwd / "GCD.v", verilog_src)
+  val fverilog = os.pwd / "GCD.v"
+  if(os.exists(fverilog))
+    os.remove(fverilog)
+  os.write(fverilog, verilog_src)
 }