Add Vivado XSim as a simulator #2363
+222
−34
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,87 @@ | ||
| proc lshift listVar { | ||
| upvar 1 $listVar L | ||
| set r [lindex $L 0] | ||
| set L [lreplace $L [set L 0] 0] | ||
| return $r | ||
| } | ||
|
|
||
| #------------------------------------------------------- | ||
| # Process command line arguments | ||
| #------------------------------------------------------- | ||
| set error 0 | ||
| set help 0 | ||
| set cycle_limit 50000 | ||
| set data "" | ||
| set verilog {} | ||
| set args $argv | ||
| # if {[llength $args] == 0} { incr help }; # Uncomment if necessary | ||
| while {[llength $args]} { | ||
| set flag [lshift args] | ||
| switch -exact -- $flag { | ||
| -i - | ||
| -ip-tcl { | ||
| set ip_script [lshift args] | ||
| } | ||
| -d - | ||
| -data { | ||
| set data [lshift args] | ||
| } | ||
| -c - | ||
| -cycle-limit { | ||
| set cycle_limit [lshift args] | ||
| } | ||
| -h - | ||
| -help { | ||
| incr help | ||
| } | ||
| default { | ||
| if {[string match "-*" $flag]} { | ||
| puts " ERROR - option '$flag' is not a valid option." | ||
| incr error | ||
| } else { | ||
| lappend verilog $flag | ||
| } | ||
| } | ||
| } | ||
| } | ||
|
|
||
| if {$help} { | ||
| set callerflag [lindex [info level [expr [info level] -1]] 0] | ||
| # <-- HELP | ||
| puts [format { | ||
| Usage: %s | ||
| [-ports|-p <listOfPorts>] | ||
| [-verbose|-v] | ||
| [-help|-h] | ||
|
|
||
| Description: xxxxxxxxxxxxxxxxxxx. | ||
| xxxxxxxxxxxxxxxxxxx. | ||
|
There was a problem hiding this comment. We should probably provide a helpful description for this script here. |
||
|
|
||
| Example: | ||
| %s -port xxxxxxxxxxxxxxx | ||
|
|
||
| } $callerflag $callerflag ] | ||
| # HELP --> | ||
| return -code ok {} | ||
| } | ||
|
|
||
| # Check validity of arguments. Increment $error to generate an error | ||
|
|
||
| if {$error} { | ||
| return -code error {Oops, something is not correct} | ||
| } | ||
|
|
||
| set dir [pwd] | ||
|
|
||
| create_project -force prj1 | ||
| add_files $verilog | ||
| if {[info exists ip_script]} { | ||
| source $ip_script | ||
| } | ||
| set_property top toplevel [get_fileset sim_1] | ||
| set_property -name {xsim.simulate.runtime} -value {all} -objects [get_filesets sim_1] | ||
| puts $cycle_limit | ||
| set_property verilog_define [subst {CYCLE_LIMIT=$cycle_limit DATA=$dir/$data}] [get_filesets sim_1] | ||
| launch_simulation | ||
| close_project | ||
| return -code ok {} | ||
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,85 @@ | ||
| import "rtl_sim" as sim; | ||
| import "testbench" as tb; | ||
| import "calyx" as c; | ||
|
|
||
| export const xsim_setup = xsim_setup; | ||
| fn xsim_setup(e) { | ||
| e.config_var("vivado-dir", "xilinx.vivado"); | ||
| e.config_var_or("cycle-limit", "sim.cycle_limit", "500000000"); | ||
| e.rsrc("xsim.tcl"); | ||
| let has_tcl = !e.config_or("xsim.ip_tcl", "").is_empty(); | ||
| if has_tcl { | ||
| let tcl_name = e.config_val("xsim.ip_tcl"); | ||
| let tcl_path = e.external_path(tcl_name); | ||
| e.var_("ip_tcl", tcl_path); | ||
| print(tcl_path); | ||
| e.rule( | ||
| "xsim-standalone-tb", | ||
| "$vivado-dir/bin/vivado -mode batch -source xsim.tcl -tclargs -c $cycle-limit -d $datadir -i $ip_tcl tb.sv verilog.sv > $out", | ||
| ); | ||
| e.rule( | ||
| "xsim-custom-tb", | ||
| "$vivado-dir/bin/vivado -mode batch -source xsim.tcl -tclargs -c $cycle-limit -d $datadir -i $ip_tcl tb.sv verilog.sv memories.sv > $out", | ||
| ); | ||
| } else { | ||
| e.rule( | ||
| "xsim-standalone-tb", | ||
| "$vivado-dir/bin/vivado -mode batch -source xsim.tcl -tclargs -c $cycle-limit -d $datadir tb.sv verilog.sv > $out", | ||
| ); | ||
| e.rule( | ||
| "xsim-custom-tb", | ||
| "$vivado-dir/bin/vivado -mode batch -source xsim.tcl -tclargs -c $cycle-limit -d $datadir tb.sv verilog.sv memories.sv > $out", | ||
| ); | ||
| } | ||
| } | ||
|
|
||
| export const xsim_build = xsim_build; | ||
| fn xsim_build(e, input, output, datadir, standalone_tb) { | ||
| if standalone_tb { | ||
| e.build_cmd( | ||
| [output], | ||
| "xsim-standalone-tb", | ||
| [input], | ||
| ["tb.sv", "xsim.tcl", datadir], | ||
| ); | ||
| } else { | ||
| e.build_cmd( | ||
| [output], | ||
| "xsim-custom-tb", | ||
| [input], | ||
| ["tb.sv", "memories.sv", "xsim.tcl", datadir], | ||
| ); | ||
| } | ||
| } | ||
|
|
||
| op( | ||
| "xsim", | ||
| [sim::sim_setup, tb::standalone_setup, xsim_setup], | ||
| c::verilog_state, | ||
| sim::dat, | ||
| |e, input, output| { | ||
| xsim_build(e, input, "sim.log", "$datadir", true); | ||
| e.build_cmd( | ||
| [output], | ||
| "json-data", | ||
| ["$datadir", "sim.log"], | ||
| ["json-dat.py"], | ||
| ); | ||
| }, | ||
| ); | ||
|
|
||
| op( | ||
| "xsim-refmem", | ||
| [sim::sim_setup, tb::custom_setup, xsim_setup], | ||
| tb::verilog_refmem, | ||
| sim::dat, | ||
| |e, input, output| { | ||
| xsim_build(e, input, "sim.log", "$datadir", false); | ||
| e.build_cmd( | ||
| [output], | ||
| "json-data", | ||
| ["$datadir", "sim.log"], | ||
| ["json-dat.py"], | ||
| ); | ||
| } | ||
| ); |
Oops, something went wrong.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Can you explain this change? On the face of it, it is turning combinational logic into sequential logic and I'm not sure why I would expect this to be correct?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Yeah this has to do with the difference between cycle based simulators like verilator (and icarus) and time step based simulators (like xsim and modelsim). Cycle based simulators evaluate all assignments in a cycle first and then all asserts. Time step based simulators progress through assignments in continuous small time steps, meaning all values in the cycle may not be evaluated before the asserts are evaluated. At some point during the cycle while evaluations are occurring it might be the case that one one-hot value has updated but another hasn't (essentially like a propagation delay) which results in multiple values being high at the same time. Basically checking the asserts combinationally is too strict for a timing based simulator to be able to handle properly. This version should also behave nearly identically on cycle based simulators because the entire cycle is evaluated before asserts are.