remove extra ap_clk ports in axi_generator.py

calyxir · Jan 2, 2025 · a5e858a · a5e858a
1 parent 24bf507
commit a5e858a
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/yxi/axi-calyx/axi_generator.py b/yxi/axi-calyx/axi_generator.py
@@ -507,8 +507,6 @@ def add_main_comp(prog, mems):
         ]
 
         add_comp_ports(wrapper_comp, wrapper_inputs, wrapper_outputs)
-        # Naming the clock signal `ap_clk` ensures Xilinx tool compatability
-        wrapper_comp.input("ap_clk", 1, ["clk"])
 
         # Cells
         # Read stuff