polyphon demo working again on rev2, temp remove usb

example-colorlight-i5.py

@@ -27,38 +27,28 @@
 from rtl.dma_router import *
 
 _io_eurolut_proto1 = [
-    ("eurorack_pmod_p6a", 0,
+    ("eurorack_pmod_aux3", 0,
         # Global clock buffer through 74HC245PW,118
         Subsignal("mclk",    Pins("J16")),
         Subsignal("bick",    Pins("L5")),
         Subsignal("lrck",    Pins("M4")),
         Subsignal("pdn",     Pins("R3")),
-        # Local signals PMOD0
-        Subsignal("i2c_sda", Pins("L4")),
-        Subsignal("i2c_scl", Pins("N4")),
-        Subsignal("sdin1",   Pins("J18")),
-        Subsignal("sdout1",  Pins("P16")),
+        # Local signals AUX3
+        Subsignal("i2c_sda", Pins("D2")),
+        Subsignal("i2c_scl", Pins("E2")),
+        Subsignal("sdin1",   Pins("A3")),
+        Subsignal("sdout1",  Pins("B1")),
         IOStandard("LVCMOS33")
     ),
-   ("ulpi", 0,
-       Subsignal("data",  Pins("D18 G5 F5 E5 D17 D16 E6 F4")),
-       Subsignal("clk",   Pins("W1")),
-       Subsignal("dir",   Pins("E16")),
-       Subsignal("nxt",   Pins("E17")),
-       Subsignal("stp",   Pins("R1")),
-       Subsignal("rst",   Pins("U1")),
-       IOStandard("LVCMOS33"),Misc("SLEWRATE=FAST")
-   ),
-   # ULPI wiring on proto1 is completely borked on schematic, below is correct for proto1 :)
-   #("ulpi", 0,
-   #    Subsignal("data",  Pins("E17 R1 E16 F4 E6 D16 D17 E5")),
-   #    Subsignal("clk",   Pins("W1")),
-   #    Subsignal("dir",   Pins("F5")),
-   #    Subsignal("nxt",   Pins("D18")),
-   #    Subsignal("stp",   Pins("G5")),
-   #    Subsignal("rst",   Pins("U1")),
-   #    IOStandard("LVCMOS33"),Misc("SLEWRATE=FAST")
-   #),
+    ("ulpi", 0,
+        Subsignal("data",  Pins("D18 G5 F5 E5 D17 D16 E6 F4")),
+        Subsignal("clk",   Pins("W1")),
+        Subsignal("dir",   Pins("E16")),
+        Subsignal("nxt",   Pins("E17")),
+        Subsignal("stp",   Pins("R1")),
+        Subsignal("rst",   Pins("U1")),
+        IOStandard("LVCMOS33"),Misc("SLEWRATE=FAST")
+    ),
     ("oled_spi", 0,
         Subsignal("clk",  Pins("Y2")),
         Subsignal("mosi", Pins("N2")),
@@ -87,17 +77,6 @@
         Subsignal("oan", Pins("G3"), Misc("PULLMODE=DOWN")),
         IOStandard("LVCMOS33")
     ),
-    ("pmod_aux1", 0,
-        Subsignal("p5", Pins("N17")),
-        Subsignal("p6", Pins("N18")),
-        Subsignal("p7", Pins("M18")),
-        Subsignal("p8", Pins("L20")),
-        Subsignal("p9", Pins("L18")),
-        Subsignal("p10", Pins("K20")),
-        Subsignal("p11", Pins("J20")),
-        Subsignal("p12", Pins("G20")),
-        IOStandard("LVCMOS33")
-    ),
     # This is pin 27 of the B50612D (top ethernet PHY), which is pretty easy to
     # bodge over to the side of R106 closest to the ECP5 so we get multiboot.
     # I removed R86 so the PHY is disconnected.
@@ -219,7 +198,6 @@ def add_encoder(soc):
     # Create logic for decoding IQ rotation
     rotary_encoder = RotaryEncoder(pads.a, pads.b)
     soc.add_module("rotary_encoder", rotary_encoder)
-    pmod_aux = soc.platform.request("pmod_aux1")
 
 def add_programn_gpio(soc):
     programp = Signal()
@@ -287,7 +265,7 @@ def main():
 
     add_audio_clocks(soc)
 
-    add_eurorack_pmod_shifter(soc, pads="eurorack_pmod_p6a", mod_name="eurorack_pmod0")
+    add_eurorack_pmod_shifter(soc, pads="eurorack_pmod_aux3", mod_name="eurorack_pmod0")
 
     add_oled(soc)
 

firmware/litex-fw/src/draw.rs

@@ -37,7 +37,7 @@ where
 
     // Channel title
     Text::with_alignment(
-        &title,
+        title,
         Point::new(top_left.x + (size.width as i32)/2, top_left.y + font_height),
         character_style_h,
         Alignment::Center,
@@ -63,11 +63,6 @@ where
         .stroke_width(1)
         .build();
 
-    let mut stroke_idle = PrimitiveStyleBuilder::new()
-        .stroke_color(Gray4::new(0x1))
-        .stroke_width(1)
-        .build();
-
     s.clear();
     if voice.state != VoiceState::Idle {
         let semitones = voice.note as i32 - 60i32;
@@ -80,11 +75,6 @@ where
             .stroke_color(Gray4::new((15f32 * voice.amplitude) as u8))
             .stroke_width(1)
             .build();
-
-        stroke_idle = PrimitiveStyleBuilder::new()
-            .stroke_color(Gray4::WHITE)
-            .stroke_width(1)
-            .build();
     }
 
     // Pitch text + box

firmware/litex-fw/src/main.rs

@@ -161,9 +161,11 @@ fn timer0_handler(state: &Mutex<RefCell<State>>, opts: &Mutex<RefCell<opt::Optio
         let opts = &mut opts.borrow_ref_mut(cs);
         state.trace.start(&timer);
         state.tick(opts, uptime_ms);
+        /*
         unsafe {
             tud_task();
         }
+        */
         state.trace.end(&timer);
     });
 }
@@ -187,6 +189,7 @@ unsafe fn irq_handler() {
         fence();
     }
 
+    /*
     // TODO: grab these correctly from PAC!
     // These are already in the SVD as constants, but not as
     // sub-nodes of the peripheral parents, so they aren't
@@ -197,13 +200,13 @@ unsafe fn irq_handler() {
     let irq_usb_in_ep  = 4usize;
     let irq_usb_out_ep = 5usize;
 
-    if ((pending_irq & (1 << irq_usb_device)) != 0 ||
-        (pending_irq & (1 << irq_usb_setup)) != 0 ||
-        (pending_irq & (1 << irq_usb_in_ep)) != 0 ||
-        (pending_irq & (1 << irq_usb_out_ep)) != 0) {
+    if (pending_irq & (1 << irq_usb_device)) != 0 ||
+       (pending_irq & (1 <<  irq_usb_setup)) != 0 ||
+       (pending_irq & (1 <<  irq_usb_in_ep)) != 0 ||
+       (pending_irq & (1 << irq_usb_out_ep)) != 0 {
         dcd_int_handler(0);
     }
-
+    */
 }
 
 struct State {
@@ -369,14 +372,6 @@ fn main() -> ! {
 
     let mut trace_main = Trace::new();
 
-    unsafe {
-        // TODO: Issue device reset before init!
-        // strategy: build statically-linked C bindings
-        // in rs-sys crate such that we don't have to
-        // manually inject the amaranth constants.
-        tusb_init();
-    }
-
     handler!(dma_router0 = || dma_router0_handler(&dma_router, &oscope));
     handler!(timer0 = || timer0_handler(&state, &opts));
 
@@ -385,10 +380,17 @@ fn main() -> ! {
         scope.register(Interrupt::DMA_ROUTER0, dma_router0);
         scope.register(Interrupt::TIMER0, timer0);
 
+        timer.set_periodic_event(TICK_MS);
+
         unsafe {
-            // Enable interrupts from DMA router (vexriscv specific register)
+
             vexriscv::register::vmim::write((1 << (pac::Interrupt::DMA_ROUTER0 as usize)) |
-                                            (1 << (pac::Interrupt::TIMER0 as usize)) );
+                                            (1 << (pac::Interrupt::TIMER0 as usize)));
+
+            /*
+            // Also enables USB interrupts
+            tusb_init();
+            */
 
             // Enable machine external interrupts (basically everything added on by LiteX).
             riscv::register::mie::set_mext();
@@ -399,8 +401,6 @@ fn main() -> ! {
             riscv::interrupt::enable();
         }
 
-        timer.set_periodic_event(TICK_MS);
-
         loop {
 
             trace_main.start(&timer);