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riscv-rt to submodule, enable single-hart option for bigger stack
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vk2seb committed Dec 5, 2023
1 parent e1a9145 commit 224bf6f
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Showing 5 changed files with 67 additions and 42 deletions.
3 changes: 3 additions & 0 deletions .gitmodules
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Expand Up @@ -70,3 +70,6 @@
[submodule "firmware/deps/tinyusb-sys-rs"]
path = firmware/deps/tinyusb-sys-rs
url = [email protected]:schnommus/tinyusb-sys-rs.git
[submodule "firmware/deps/riscv-rt"]
path = firmware/deps/riscv-rt
url = http://github.com/rust-embedded/riscv-rt
1 change: 1 addition & 0 deletions firmware/deps/riscv-rt
Submodule riscv-rt added at f04d16
94 changes: 56 additions & 38 deletions firmware/litex-fw/Cargo.lock

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2 changes: 1 addition & 1 deletion firmware/litex-fw/Cargo.toml
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Expand Up @@ -15,7 +15,7 @@ path = "src/main.rs"

[dependencies]
riscv = { version = "*", features = ["critical-section-single-hart"] }
riscv-rt = "*"
riscv-rt = { path = "../deps/riscv-rt", features = ["single-hart"] }
litex-hal = { path = "../deps/rust-litex-hal", features = ["gpio"] }
litex-pac = { path = "../litex-pac", features = ["rt"] }
ssd1322 = { path = "../ssd1322", features = [] }
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9 changes: 6 additions & 3 deletions firmware/litex-fw/src/main.rs
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Expand Up @@ -338,8 +338,8 @@ pub extern "C" fn tud_dfu_get_timeout_cb(_alt: u8, state: u8) -> u32 {
}

#[no_mangle]
pub extern "C" fn tud_dfu_download_cb(_alt: u8, block_num: u16, data: *const u8, length: u16) {
// TODO
pub extern "C" fn tud_dfu_download_cb(alt: u8, block_num: u16, data: *const u8, length: u16) {
log::info!("DOWNLOAD alt={} block_num={} len={}", alt, block_num, length);
unsafe {
tud_dfu_finish_flashing(dfu_status_t::DFU_STATUS_OK as u8);
}
Expand Down Expand Up @@ -423,10 +423,13 @@ fn main() -> ! {
// Enable machine external interrupts (basically everything added on by LiteX).
riscv::register::mie::set_mext();

// WARN: delay before interrupt enable after tusb_init(), the USB core takes a while
// to spin up after tusb_init() if nothing is connected, apparently.
timer.delay_ms(100u32);

// WARN: Don't do this before IRQs are registered for this scope,
// otherwise you'll hang forever :)
// Finally enable interrupts
timer.delay_ms(100u32);
riscv::interrupt::enable();
}

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