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Add tests
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Signed-off-by: Ryszard Rozak <[email protected]>
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RRozak committed Dec 13, 2024
1 parent c1a2c37 commit bef3556
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21 changes: 21 additions & 0 deletions test_regress/t/t_randomize_param_with.py
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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('simulator')

if not test.have_solver:
test.skip("No constraint solver installed")

test.compile()

test.execute()

test.passes()
51 changes: 51 additions & 0 deletions test_regress/t/t_randomize_param_with.v
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0

`define check_rand(cl, field, constr, cond) \
begin \
longint prev_result; \
int ok = 0; \
if (!bit'(cl.randomize() with { constr; })) $stop; \
prev_result = longint'(field); \
if (!(cond)) $stop; \
repeat(9) begin \
longint result; \
if (!bit'(cl.randomize() with { constr; })) $stop; \
result = longint'(field); \
if (!(cond)) $stop; \
if (result != prev_result) ok = 1; \
prev_result = result; \
end \
if (ok != 1) $stop; \
end

class Cls #(int LIMIT = 3);
rand int x;
int y = -100;
constraint x_limit { x <= LIMIT; };
endclass

module t;
initial begin
Cls#() cd = new;
Cls#(5) c5 = new;
int y = 2;

`check_rand(cd, cd.x, x > 0, cd.x > 0 && cd.x <= 3);
`check_rand(cd, cd.x, x > y, cd.x > -100 && cd.x <= 3);
`check_rand(cd, cd.x, x > local::y, cd.x > 2 && cd.x <= 3);
if (cd.randomize() with {x > 3;} == 1) $stop;

`check_rand(c5, c5.x, x > 0, c5.x > 0 && c5.x <= 5);
`check_rand(c5, c5.x, x > y, c5.x > -100 && c5.x <= 5);
`check_rand(c5, c5.x, x > local::y, c5.x > 2 && c5.x <= 5);
if (c5.randomize() with {x >= 5;} == 0) $stop;
if (c5.x != 5) $stop;

$write("*-* All Finished *-*\n");
$finish;
end
endmodule

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