Add test for iff in assert sensitivity

Signed-off-by: Krzysztof Bieganski <[email protected]>

test_regress/t/t_assert_iff.pl

@@ -0,0 +1,38 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert --cc --coverage-user -DFAIL1'],
+    );
+
+execute(
+    fails => 1,
+    );
+
+compile(
+    verilator_flags2 => ['--assert --cc --coverage-user -DFAIL2'],
+    );
+
+execute(
+    fails => 1,
+    );
+
+compile(
+    verilator_flags2 => ['--assert --cc --coverage-user'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_iff.v

@@ -0,0 +1,57 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   logic[3:0] enable;
+   int cyc = 0;
+
+   Test test(.*);
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      `ifdef FAIL1 enable[0] <= 1; `endif
+      enable[1] <= 1;
+      `ifdef FAIL2 enable[2] <= 1; `endif
+      enable[3] <= 1;
+      if (cyc != 0) begin
+         if (cyc == 10) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+         end
+      end
+   end
+endmodule
+
+module Test(
+   input clk,
+   input[3:0] enable
+   );
+
+   assert property (
+     @(posedge clk iff enable[0])
+     0
+   ) else $stop;
+
+   assert property (
+     @(posedge clk iff enable[1])
+     1
+   );
+
+   cover property (
+     @(posedge clk iff enable[2])
+     1
+   ) $stop;
+
+   cover property (
+     @(posedge clk iff enable[3])
+     0
+   ) $stop;
+
+endmodule