Do not emit BLKSEQ on suspendable non-sequential process

Signed-off-by: Krzysztof Bieganski <[email protected]>
antmicro · Jan 8, 2025 · 3992adb · 3992adb
1 parent ff244c1
commit 3992adb
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Showing 3 changed files with 13 additions and 18 deletions.
diff --git a/src/V3Active.cpp b/src/V3Active.cpp
@@ -349,7 +349,7 @@ class ActiveLatchCheckVisitor final : public VNVisitorConst {
 
 class ActiveDlyVisitor final : public VNVisitor {
 public:
-    enum CheckType : uint8_t { CT_SEQ, CT_COMB, CT_INITIAL };
+    enum CheckType : uint8_t { CT_SEQ, CT_COMB, CT_INITIAL, CT_SUSPENDABLE };
 
 private:
     // MEMBERS
@@ -358,7 +358,7 @@ class ActiveDlyVisitor final : public VNVisitor {
     // VISITORS
     void visit(AstAssignDly* nodep) override {
         // Non-blocking assignments are OK in sequential processes
-        if (m_check == CT_SEQ) return;
+        if (m_check == CT_SEQ || m_check == CT_SUSPENDABLE) return;
 
         // Issue appropriate warning
         if (m_check == CT_INITIAL) {
@@ -479,19 +479,20 @@ class ActiveVisitor final : public VNVisitor {
               : oldsensesp      ? m_namer.getActive(nodep->fileline(), oldsensesp)
                                 : m_namer.getSpecialActive<AstSenItem::Initial>(nodep->fileline());
 
-        // Delete sensitivity list
-        if (oldsensesp) VL_DO_DANGLING(oldsensesp->deleteTree(), oldsensesp);
-
         // Move node to new active
         nodep->unlinkFrBack();
         wantactivep->addStmtsp(nodep);
 
         // Warn and convert any delayed assignments
         {
-            ActiveDlyVisitor{nodep, m_clockedProcess ? ActiveDlyVisitor::CT_SEQ
-                                                     : ActiveDlyVisitor::CT_COMB};
+            ActiveDlyVisitor{nodep, !m_clockedProcess ? ActiveDlyVisitor::CT_COMB
+                                    : oldsensesp      ? ActiveDlyVisitor::CT_SEQ
+                                                      : ActiveDlyVisitor::CT_SUSPENDABLE};
         }
 
+        // Delete sensitivity list
+        if (oldsensesp) VL_DO_DANGLING(oldsensesp->deleteTree(), oldsensesp);
+
         // check combinational processes for latches
         if (!m_clockedProcess || kwd == VAlwaysKwd::ALWAYS_LATCH) {
             const ActiveLatchCheckVisitor latchvisitor{nodep, kwd == VAlwaysKwd::ALWAYS_LATCH};

diff --git a/test_regress/t/t_timing_clkgen2.py b/test_regress/t/t_timing_clkgen2.py
@@ -11,7 +11,7 @@
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["--exe --main --timing"])
+test.compile(verilator_flags2=["--exe --main --timing -Wwarn-BLKSEQ"])
 
 test.execute()
 

diff --git a/test_regress/t/t_timing_clkgen2.v b/test_regress/t/t_timing_clkgen2.v
@@ -17,24 +17,18 @@ module t;
    int   cnt2 = 0;
 
    always #4 clk = ~clk;
-   always @(negedge clk) begin
-       cnt1++;
-       `WRITE_VERBOSE(("[%0t] NEG clk (%b)\n", $time, clk));
-   end
    always @(posedge clk) begin
-       cnt1++;
-       `WRITE_VERBOSE(("[%0t] POS clk (%b)\n", $time, clk));
+       cnt1 <= cnt1 + 1;
+       `WRITE_VERBOSE(("[%0t] clk (%b)\n", $time, clk));
    end
 
    assign #2 clk_inv = ~clk;
    initial forever begin
        @(posedge clk_inv) cnt2++;
-       `WRITE_VERBOSE(("[%0t] POS clk_inv (%b)\n", $time, clk_inv));
-       @(negedge clk_inv) cnt2++;
-       `WRITE_VERBOSE(("[%0t] NEG clk_inv (%b)\n", $time, clk_inv));
+       `WRITE_VERBOSE(("[%0t] clk_inv (%b)\n", $time, clk_inv));
    end
 
-   initial #41 begin
+   initial #81 begin
        if (cnt1 != 10 && cnt2 != 10) $stop;
        $write("*-* All Finished *-*\n");
        $finish;