Add a regression test

Signed-off-by: Krzysztof Boronski <[email protected]>

test_regress/t/t_selextract_in_paramextends.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--timing"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_selextract_in_paramextends.v

@@ -0,0 +1,44 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef class Foo;
+
+virtual class Bar #(type T);
+  T m_val;
+endclass
+
+class Baz;
+  rand bit [3:0] m_sus;
+endclass
+
+class Foo extends Bar#(Baz);
+  function new();
+    Baz baz;
+    super.new();
+    baz = new;
+    super.m_val = baz;
+  endfunction
+
+  task update_value(Foo foo, bit [1:0] val);
+    m_val.m_sus[1:0] = val;
+  endtask
+endclass
+
+module test();
+  initial begin
+    Foo foo = new;
+
+    for (int i = 0; i < 10; i++) begin
+      logic [3:0] v;
+      foo.update_value(foo, i[1:0]);
+      v = foo.m_val.m_sus;
+      if (v[1:0] != i[1:0]) $stop;
+    end
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule