Do not remap local assign intravals in forks

Signed-off-by: Krzysztof Bieganski <[email protected]>

src/V3SchedTiming.cpp

@@ -293,7 +293,7 @@ void transformForks(AstNetlist* const netlistp) {
                 AstVar* const varp = refp->varp();
                 AstBasicDType* const dtypep = varp->dtypep()->basicp();
                 bool passByValue = false;
-                if (VString::startsWith(varp->name(), "__Vintra")) {
+                if (!varp->isFuncLocal() && VString::startsWith(varp->name(), "__Vintra")) {
                     // Pass it by value to the new function, as otherwise there are issues with
                     // -flocalize (see t_timing_intra_assign)
                     passByValue = true;

test_regress/t/t_fork_jumpblock.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    make_main => 0,
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_fork_jumpblock.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+class bar;
+    task foo(logic r);
+        int a, b;
+        if (r) return;
+        fork a = #1 b; join_none
+    endtask
+endclass
+
+module t;
+    bar b = new;
+
+    initial begin
+        b.foo(0);
+        $write("*-* All Finished *-*\n");
+        $finish;
+    end
+endmodule