update d939734

.buildinfo

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+# Sphinx build info version 1
+# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done.
+config: 5c068968cf9234262e446c481a46d2c1
+tags: 645f666f9bcd5a90fca523b33c5a78b7

_sources/arty.md.txt

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+# Arty-A7 board
+
+The [Arty-A7 board](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) allows testing its on-board DDR3 module.
+The board is designed around the Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx.
+
+```{image} images/arty-a7.jpg
+```
+
+The following instructions explain how to set up the board.
+
+## Board configuration
+
+Connect the board USB and Ethernet cables to your computer and configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address.
+Next, generate the FPGA bitstream:
+
+```sh
+export TARGET=arty
+make build
+```
+
+```{note}
+This will by default target Arty A7 with the XC7A35TICSG324-1L FPGA. To build for XC7A100TCSG324-1,
+use `make build TARGET_ARGS="--variant a7-100"`
+```
+
+The results will be located in: `build/arty/gateware/digilent_arty.bit`. To upload it, use:
+
+```sh
+export TARGET=arty
+make upload
+```
+
+```{note}
+By typing `make` (without `build`) LiteX will generate build files without invoking Vivado.
+```
+
+To save bitstream in flash memory, use:
+
+```sh
+export TARGET=arty
+make flash
+```
+
+Bitstream will be loaded from flash memory upon device power-on or after a PROG button press.

_sources/build/arty/documentation/controller_settings.rst.txt

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+CONTROLLER_SETTINGS
+===================
+
+Allows to change LiteDRAMController behaviour at runtime
+--------------------------------------------------------
+
+
+Register Listing for CONTROLLER_SETTINGS
+----------------------------------------
+
++------------------------------------------------------------------+-------------------------------------------------+
+| Register                                                         | Address                                         |
++==================================================================+=================================================+
+| :ref:`CONTROLLER_SETTINGS_REFRESH <CONTROLLER_SETTINGS_REFRESH>` | :ref:`0xf0001000 <CONTROLLER_SETTINGS_REFRESH>` |
++------------------------------------------------------------------+-------------------------------------------------+
+
+CONTROLLER_SETTINGS_REFRESH
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+`Address: 0xf0001000 + 0x0 = 0xf0001000`
+
+    Enable/disable Refresh commands sending
+
+    .. wavedrom::
+        :caption: CONTROLLER_SETTINGS_REFRESH
+
+        {
+            "reg": [
+                {"name": "refresh", "attr": 'reset: 1', "bits": 1},
+                {"bits": 31},
+            ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
+        }
+
+

_sources/build/arty/documentation/ctrl.rst.txt

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+CTRL
+====
+
+Register Listing for CTRL
+-------------------------
+
++------------------------------------------+-------------------------------------+
+| Register                                 | Address                             |
++==========================================+=====================================+
+| :ref:`CTRL__RESET <CTRL__RESET>`         | :ref:`0xf0005000 <CTRL__RESET>`     |
++------------------------------------------+-------------------------------------+
+| :ref:`CTRL_SCRATCH <CTRL_SCRATCH>`       | :ref:`0xf0005004 <CTRL_SCRATCH>`    |
++------------------------------------------+-------------------------------------+
+| :ref:`CTRL_BUS_ERRORS <CTRL_BUS_ERRORS>` | :ref:`0xf0005008 <CTRL_BUS_ERRORS>` |
++------------------------------------------+-------------------------------------+
+
+CTRL__RESET
+^^^^^^^^^^^
+
+`Address: 0xf0005000 + 0x0 = 0xf0005000`
+
+
+    .. wavedrom::
+        :caption: CTRL__RESET
+
+        {
+            "reg": [
+                {"name": "soc_rst",  "type": 4, "bits": 1},
+                {"name": "cpu_rst",  "bits": 1},
+                {"bits": 30}
+            ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
+        }
+
+
++-------+---------+------------------------------------------------------------------------+
+| Field | Name    | Description                                                            |
++=======+=========+========================================================================+
+| [0]   | SOC_RST | Write `1` to this register to reset the full SoC (Pulse Reset)         |
++-------+---------+------------------------------------------------------------------------+
+| [1]   | CPU_RST | Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset) |
++-------+---------+------------------------------------------------------------------------+
+
+CTRL_SCRATCH
+^^^^^^^^^^^^
+
+`Address: 0xf0005000 + 0x4 = 0xf0005004`
+
+    Use this register as a scratch space to verify that software read/write accesses
+    to the Wishbone/CSR bus are working correctly. The initial reset value of
+    0x1234578 can be used to verify endianness.
+
+    .. wavedrom::
+        :caption: CTRL_SCRATCH
+
+        {
+            "reg": [
+                {"name": "scratch[31:0]", "attr": 'reset: 305419896', "bits": 32}
+            ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1}
+        }
+
+
+CTRL_BUS_ERRORS
+^^^^^^^^^^^^^^^
+
+`Address: 0xf0005000 + 0x8 = 0xf0005008`
+
+    Total number of Wishbone bus errors (timeouts) since start.
+
+    .. wavedrom::
+        :caption: CTRL_BUS_ERRORS
+
+        {
+            "reg": [
+                {"name": "bus_errors[31:0]", "bits": 32}
+            ], "config": {"hspace": 400, "bits": 32, "lanes": 1 }, "options": {"hspace": 400, "bits": 32, "lanes": 1}
+        }
+
+

_sources/build/arty/documentation/ddrctrl.rst.txt

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+DDRCTRL
+=======
+
+Register Listing for DDRCTRL
+----------------------------
+
++------------------------------------------------+----------------------------------------+
+| Register                                       | Address                                |
++================================================+========================================+
+| :ref:`DDRCTRL_INIT_DONE <DDRCTRL_INIT_DONE>`   | :ref:`0xf0001800 <DDRCTRL_INIT_DONE>`  |
++------------------------------------------------+----------------------------------------+
+| :ref:`DDRCTRL_INIT_ERROR <DDRCTRL_INIT_ERROR>` | :ref:`0xf0001804 <DDRCTRL_INIT_ERROR>` |
++------------------------------------------------+----------------------------------------+
+
+DDRCTRL_INIT_DONE
+^^^^^^^^^^^^^^^^^
+
+`Address: 0xf0001800 + 0x0 = 0xf0001800`
+
+
+    .. wavedrom::
+        :caption: DDRCTRL_INIT_DONE
+
+        {
+            "reg": [
+                {"name": "init_done", "bits": 1},
+                {"bits": 31},
+            ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
+        }
+
+
+DDRCTRL_INIT_ERROR
+^^^^^^^^^^^^^^^^^^
+
+`Address: 0xf0001800 + 0x4 = 0xf0001804`
+
+
+    .. wavedrom::
+        :caption: DDRCTRL_INIT_ERROR
+
+        {
+            "reg": [
+                {"name": "init_error", "bits": 1},
+                {"bits": 31},
+            ], "config": {"hspace": 400, "bits": 32, "lanes": 4 }, "options": {"hspace": 400, "bits": 32, "lanes": 4}
+        }
+
+