Veriblelint: Support waivers

Since chipsalliance/verible#293 Verible lint supports
(multiple) waiver files; add support for that to edalize.

I didn't add any version detection for Verible since we're currently
assuming `master` of Verible for edalize, as long as Verible hasn't done
a stable release yet.

Fixes chipsalliance#153

edalize/veriblelint.py

@@ -50,13 +50,16 @@ def run_main(self):
 
         src_files_filtered = []
         config_files_filtered = []
+        waiver_files_filtered = []
         for src_file in src_files:
             ft = src_file.file_type
 
             if ft.startswith("verilogSource") or ft.startswith("systemVerilogSource"):
                src_files_filtered.append(src_file.name)
-            elif ft.startswith("veribleLintRules"):
+            elif ft == "veribleLintRules":
                config_files_filtered.append(src_file.name)
+            elif ft == "veribleLintWaiver":
+               waiver_files_filtered.append(src_file.name)
 
         if len(src_files_filtered) == 0:
             logger.warning("No SystemVerilog source files to be processed.")
@@ -65,9 +68,11 @@ def run_main(self):
         lint_fail = False
         args = self._get_tool_args()
         if len(config_files_filtered) > 1:
-            raise RuntimeError("Too many Verible lint rule files specified")
+            raise RuntimeError("Verible lint only supports a single rules file (type veribleLintRules)")
         elif len(config_files_filtered) == 1:
             args.append('--rules_config=' + config_files_filtered[0])
+        if waiver_files_filtered:
+            args.append('--waiver_files=' + ','.join(waiver_files_filtered))
 
         for src_file in src_files_filtered:
             cmd = ['verilog_lint'] + args + [src_file]

tests/edalize_common.py

@@ -177,29 +177,31 @@ def _setup_backend(name, tool, paramtypes, files,
 
 
 FILES = [
-    {'name' : 'qip_file.qip' , 'file_type' : 'QIP'},
-    {'name' : 'qsys_file'    , 'file_type' : 'QSYS'},
-    {'name' : 'sdc_file'     , 'file_type' : 'SDC'},
-    {'name' : 'bmm_file'     , 'file_type' : 'BMM'},
-    {'name' : 'sv_file.sv'   , 'file_type' : 'systemVerilogSource'},
-    {'name' : 'pcf_file.pcf' , 'file_type' : 'PCF'},
-    {'name' : 'ucf_file.ucf' , 'file_type' : 'UCF'},
-    {'name' : 'user_file'    , 'file_type' : 'user'},
-    {'name' : 'tcl_file.tcl' , 'file_type' : 'tclSource'},
-    {'name' : 'vlog_file.v'  , 'file_type' : 'verilogSource'},
-    {'name' : 'vlog05_file.v', 'file_type' : 'verilogSource-2005'},
-    {'name' : 'vlog_incfile' , 'file_type' : 'verilogSource', 'is_include_file' : True},
-    {'name' : 'vhdl_file.vhd', 'file_type' : 'vhdlSource'},
-    {'name' : 'vhdl_lfile'   , 'file_type' : 'vhdlSource', 'logical_name' : 'libx'},
-    {'name' : 'vhdl2008_file', 'file_type' : 'vhdlSource-2008'},
-    {'name' : 'xci_file.xci' , 'file_type' : 'xci'},
-    {'name' : 'xdc_file.xdc' , 'file_type' : 'xdc'},
-    {'name' : 'bootrom.mem'  , 'file_type' : 'mem'},
-    {'name' : 'c_file.c'     , 'file_type' : 'cSource'},
-    {'name' : 'cpp_file.cpp' , 'file_type' : 'cppSource'},
-    {'name' : 'c_header.h'   , 'file_type' : 'cSource', 'is_include_file' : True},
-    {'name' : 'c_header.h'   , 'file_type' : 'cppSource', 'is_include_file' : True},
-    {'name' : 'config.vbl'   , 'file_type' : 'veribleLintRules'}
+    {"name": "qip_file.qip", "file_type": "QIP"},
+    {"name": "qsys_file", "file_type": "QSYS"},
+    {"name": "sdc_file", "file_type": "SDC"},
+    {"name": "bmm_file", "file_type": "BMM"},
+    {"name": "sv_file.sv", "file_type": "systemVerilogSource"},
+    {"name": "pcf_file.pcf", "file_type": "PCF"},
+    {"name": "ucf_file.ucf", "file_type": "UCF"},
+    {"name": "user_file", "file_type": "user"},
+    {"name": "tcl_file.tcl", "file_type": "tclSource"},
+    {"name": "vlog_file.v", "file_type": "verilogSource"},
+    {"name": "vlog05_file.v", "file_type": "verilogSource-2005"},
+    {"name": "vlog_incfile", "file_type": "verilogSource", "is_include_file": True},
+    {"name": "vhdl_file.vhd", "file_type": "vhdlSource"},
+    {"name": "vhdl_lfile", "file_type": "vhdlSource", "logical_name": "libx"},
+    {"name": "vhdl2008_file", "file_type": "vhdlSource-2008"},
+    {"name": "xci_file.xci", "file_type": "xci"},
+    {"name": "xdc_file.xdc", "file_type": "xdc"},
+    {"name": "bootrom.mem", "file_type": "mem"},
+    {"name": "c_file.c", "file_type": "cSource"},
+    {"name": "cpp_file.cpp", "file_type": "cppSource"},
+    {"name": "c_header.h", "file_type": "cSource", "is_include_file": True},
+    {"name": "c_header.h", "file_type": "cppSource", "is_include_file": True},
+    {"name": "config.vbl", "file_type": "veribleLintRules"},
+    {"name": "verible_waiver.vbw", "file_type": "veribleLintWaiver"},
+    {"name": "verible_waiver2.vbw", "file_type": "veribleLintWaiver"},
 ]
 """Files of all supported file types."""
 

tests/test_veriblelint/lint/verilog_lint.cmd

@@ -1,3 +1,3 @@
---lint_fatal --parse_fatal --rules_config=config.vbl sv_file.sv
---lint_fatal --parse_fatal --rules_config=config.vbl vlog_file.v
---lint_fatal --parse_fatal --rules_config=config.vbl vlog05_file.v
+--lint_fatal --parse_fatal --rules_config=config.vbl --waiver_files=verible_waiver.vbw,verible_waiver2.vbw sv_file.sv
+--lint_fatal --parse_fatal --rules_config=config.vbl --waiver_files=verible_waiver.vbw,verible_waiver2.vbw vlog_file.v
+--lint_fatal --parse_fatal --rules_config=config.vbl --waiver_files=verible_waiver.vbw,verible_waiver2.vbw vlog05_file.v

tests/test_vivado/test_vivado_0.tcl

@@ -27,6 +27,8 @@ read_mem bootrom.mem
 add_files -norecurse c_file.c
 add_files -norecurse cpp_file.cpp
 add_files -norecurse config.vbl
+add_files -norecurse verible_waiver.vbw
+add_files -norecurse verible_waiver2.vbw
 
 set_property include_dirs [list . .] [get_filesets sources_1]
 set_property top top_module [current_fileset]