ARCv2: [axs103_smp] Reduce clk for SMP FPGA configs

Newer bitfiles needs the reduced clk even for SMP builds Cc: <[email protected]> #4.2 Signed-off-by: Vineet Gupta <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
again4you · Sep 12, 2015 · 3ebb054 · 3ebb054
1 parent ded0e25
commit 3ebb054
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
@@ -402,6 +402,8 @@ static void __init axs103_early_init(void)
 	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
 	if (num_cores > 2)
 		arc_set_core_freq(50 * 1000000);
+	else if (num_cores == 2)
+		arc_set_core_freq(75 * 1000000);
 #endif
 
 	switch (arc_get_core_freq()/1000000) {