Push RISC-V Core to swim-v2 #343
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RISC-V core to a new branch. SWIM will still work even with these unfinished since the RISC-V core is being kept out of the module rs file until it's more complete and can be tested.
control signals in the datapath, minus memory operations. STILL TODO: Memory operations Adding operations Making it all work
moving onto branching and jumping handling.
Fixed some typos. datapath.rs is error-free, but must be expanded with RV64I and more.
control signals in the datapath, minus memory operations. STILL TODO: Memory operations Adding operations Making it all work
moving onto branching and jumping handling.
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Pushing the in-progress (Unfinished, not working) RISC-V core to a new branch. SWIM will still work
even with these unfinished since the RISC-V core is
being kept out of the module rs file until it's more complete
and can be tested.