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Removed log statements AGAIN.
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rharding8 committed Apr 20, 2024
1 parent 76861b7 commit ab93485
Showing 1 changed file with 0 additions and 8 deletions.
8 changes: 0 additions & 8 deletions src/emulation_core/riscv/datapath.rs
Original file line number Diff line number Diff line change
Expand Up @@ -31,8 +31,6 @@ use crate::emulation_core::stack::Stack;
use crate::emulation_core::stack::StackFrame;
use serde::{Deserialize, Serialize};

use gloo_console::log;

/// An implementation of a datapath for the MIPS64 ISA.
#[derive(Clone, PartialEq)]
pub struct RiscDatapath {
Expand Down Expand Up @@ -534,7 +532,6 @@ impl RiscDatapath {

// Set the data lines based on the contents of the instruction.
// Some lines will hold uninitialized values as a result.
log!("Current Instruction: ", format!("{:?}", self.instruction));
match self.instruction {
RiscInstruction::RType(r) => {
self.state.rs1 = r.rs1 as u32;
Expand Down Expand Up @@ -589,8 +586,6 @@ impl RiscDatapath {
fn set_immediate(&mut self) {
let mut signed_imm = 0x0000;

log!("self.state.imm: ", format!("{:012b}", self.state.imm));

signed_imm = match self.signals.imm_select {
ImmSelect::ISigned => {
let mask = 0b100000000000;
Expand All @@ -616,9 +611,6 @@ impl RiscDatapath {
ImmSelect::JType => self.state.imm,
};

log!("signed_imm: ", format!("{:?}", signed_imm));
log!("self.state.imm: ", format!("{:?}", self.state.imm));

self.state.imm = signed_imm;
}

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