Merge pull request #390 from SWIM-ucf/riscv-tests

Riscv tests and fixes
SWIM-ucf · Apr 20, 2024 · 6d3da46 · 6d3da46
2 parents f9710bc + 788706e
commit 6d3da46
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Showing 3 changed files with 977 additions and 7 deletions.
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
@@ -313,7 +313,6 @@ impl Datapath for RiscDatapath {
 
 impl RiscDatapath {
     // ===================== General Functions =====================
-
     /// Load a vector of 32-bit instructions into memory. If the process fails,
     /// from a lack of space or otherwise, an [`Err`] is returned.
     fn load_instructions(&mut self, instructions: Vec<u32>) -> Result<(), String> {
@@ -537,7 +536,7 @@ impl RiscDatapath {
                 self.state.rs1 = r.rs1 as u32;
                 self.state.rs2 = r.rs2 as u32;
                 self.state.rd = r.rd as u32;
-                self.state.shamt = r.rs2 as u32;
+                self.state.shamt = (self.registers.gpr[r.rs2 as usize] & 0b11111) as u32;
                 self.state.funct3 = r.funct3 as u32;
                 self.state.funct7 = r.funct7 as u32;
             }
@@ -676,7 +675,7 @@ impl RiscDatapath {
                 _ => (),
             },
             1 => match r.funct7 {
-                0b0000000 => self.signals.alu_op = AluOp::ShiftLeftLogical(self.state.rs2),
+                0b0000000 => self.signals.alu_op = AluOp::ShiftLeftLogical(self.state.shamt),
                 0b0000001 => self.signals.alu_op = AluOp::MultiplicationSignedUpper,
                 _ => (),
             },
@@ -696,8 +695,8 @@ impl RiscDatapath {
                 _ => (),
             },
             5 => match r.funct7 {
-                0b0000000 => self.signals.alu_op = AluOp::ShiftRightLogical(self.state.rs2),
-                0b0100000 => self.signals.alu_op = AluOp::ShiftRightArithmetic(self.state.rs2),
+                0b0000000 => self.signals.alu_op = AluOp::ShiftRightLogical(self.state.shamt),
+                0b0100000 => self.signals.alu_op = AluOp::ShiftRightArithmetic(self.state.shamt),
                 0b0000001 => self.signals.alu_op = AluOp::DivisionUnsigned,
                 _ => (),
             },
@@ -958,7 +957,7 @@ impl RiscDatapath {
             AluOp::Xor => self.state.alu_input1 ^ self.state.alu_input2,
             AluOp::ShiftLeftLogical(shamt) => self.state.alu_input1 << shamt,
             AluOp::ShiftRightLogical(shamt) => self.state.alu_input1 >> shamt,
-            AluOp::ShiftRightArithmetic(shamt) => (self.state.alu_input1 as i64 >> shamt) as u64,
+            AluOp::ShiftRightArithmetic(shamt) => ((self.state.alu_input1 as i64) >> shamt) as u64,
             AluOp::MultiplicationSigned => {
                 ((self.state.alu_input1 as i128) * (self.state.alu_input2 as i128)) as u64
             }
@@ -1058,7 +1057,7 @@ impl RiscDatapath {
     }
 
     fn calc_relative_pc_branch(&mut self) {
-        if self.state.imm > 0 {
+        if self.state.imm >= 0 {
             self.state.relative_pc_branch = self.state.imm as u64 * 4;
         }
     }

diff --git a/src/tests/emulation_core.rs b/src/tests/emulation_core.rs
@@ -2,5 +2,6 @@ pub mod memory;
 pub mod mips;
 pub mod mips_instruction;
 pub mod registers;
+pub mod riscv;
 pub mod riscv_instruction;
 pub mod riscv_registers;