Structure of common HW development framework

Structure of common HW development framework

The jungle of HW development frameworks was quite a wild place in 2018 but we can see some patterns across all frameworks. Main parts are of such a framework are:

1. Core

   • HDL - Implementation of input Hardware Description language or parser for existing HDL like Verilog

   • Internal representation of circuit/code

2. Core IO

   • Serialization library - Conversion of internal representation to target HDL.

   • Intercompatibility layer - Conversion of other HDLs to internal representation.

3. Component libs

   • Library of primitives - Contains most basic elements used by other libraries.

   • Application specific libs - like networking, IO, image processing etc.

4. Simulator/verification environment - Simulator and API for simulation processes or API for generation of testbenches.

   • API for existing RTL simulator

   • Custom simulator

   • UVM like sim. environment

5. High level programming

   • DSP, floating point, HLS support libraries - Libraries to support complex components and data types and to perform high order optimizations over circuit.

6. Buildsystem - The tool or library which puts all things together.

   • Board/chip/process support libraries - Library with informations about target chips and boards to customize result of the target platform
   • Package manager

	1.	2.	3.
hwt	hwt.code, hwt.hdl	hwt.serializer, hdlConvertor	hwtLib
chisel3	chisel3.core, chisel3.internal.firrlt	chisel3.internal.firrlt	chisel3.utils
yosys	yosys::RTLIL, verilog	yosys/frontends, yosys/backends	-

	4.	5.	6.
hwt	hwt.simulator, pycocotb	hwtHls	python packagin tools (pip, setuptools)
chisel3	chisel3.testers, chisel-iotesters	dsptools	scala packaging tools (sbt)
yosys	-	-	yosys/techlibs, c buildsystems (makefile, meson)