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Criando leitura sinclona
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Implementando sistema para espera de leitura e escrita da memoria, para
casos cuja a memoria e mais lenta que o processador, o processador
aguarda para o sinal memory_response ser 1 para prosseguir, enquanto o
mesmo for 0, ele continua em estado de espera.

Para casos de resposta imediata, basta realizar um assign do
memery_responde = merory_read | memory_write
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@JN513
JN513 committed Apr 17, 2024
1 parent e582dbb commit 4b1f2f8
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Showing 3 changed files with 127 additions and 40 deletions.
110 changes: 84 additions & 26 deletions src/core/control_unit.v
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
module Control_Unit (
input wire clk,
input wire reset,
input wire response,
input wire memory_response,
input wire [1:0] last_bits,
input wire [1:0] last_bits_saved_address,
input wire [2:0] func3,
Expand All @@ -19,6 +19,7 @@ module Control_Unit (
output reg save_address,
output reg save_value,
output reg save_value_2,
output reg save_write_value,
output reg control_memory_op,
output reg write_data_in,
output reg [1:0] lorD,
Expand Down Expand Up @@ -126,6 +127,7 @@ initial begin
write_data_in = 1'b0;
clear_hal_byte_one_block_option = 1'b0;
clear_hal_byte_one_block_option_2 = 1'b0;
save_write_value = 1'b0;
end

always @(posedge clk ) begin
Expand All @@ -138,9 +140,18 @@ end

always @(*) begin
nextstate = FETCH;
pc_write = 1'b0;
ir_write = 1'b0;
case (state)
FETCH:
nextstate = DECODE;
FETCH: begin
if(memory_response) begin
pc_write = 1'b1;
ir_write = 1'b1;
nextstate = DECODE;
end else begin
nextstate = FETCH;
end
end
DECODE: begin
case (instruction_opcode)
LW: nextstate = MEMADR;
Expand Down Expand Up @@ -169,10 +180,26 @@ always @(*) begin
nextstate = MEMWRITE;
end
end
MEMREAD: nextstate = MEMWB;
MEMREAD_UNALIGNED: nextstate = LOAD_FIRST_BLOCK;
MEMREAD: begin
if(memory_response)
nextstate = MEMWB;
else
nextstate = MEMREAD;
end
MEMREAD_UNALIGNED: begin
if(memory_response) begin
nextstate = LOAD_FIRST_BLOCK;
end else begin
nextstate = MEMREAD_UNALIGNED;
end
end
MEMWB: nextstate = FETCH;
MEMWRITE: nextstate = FETCH;
MEMWRITE: begin
if(memory_response)
nextstate = FETCH;
else
nextstate = MEMWRITE;
end
EXECUTER: nextstate = ALUWB;
ALUWB: nextstate = FETCH;
EXECUTEI: nextstate = ALUWB;
Expand All @@ -193,10 +220,22 @@ always @(*) begin
end
FILTER_ALU_WB: nextstate = FETCH;
CALC_NEXT_ADDRESS: nextstate = READ_SECOND_BLOCK;
READ_SECOND_BLOCK: nextstate = LOAD_SECOND_BLOCK;
READ_SECOND_BLOCK: begin
if(memory_response) begin
nextstate = LOAD_SECOND_BLOCK;
end else begin
nextstate = READ_SECOND_BLOCK;
end
end
LOAD_SECOND_BLOCK: nextstate = MERGE_BLOCKS;
MERGE_BLOCKS: nextstate = FILTER_ALU_WB;
MEMWRITE_UNALIGNED: nextstate = GEN_FIRST_BLOCK_PART_1;
MEMWRITE_UNALIGNED: begin
if(memory_response) begin
nextstate = GEN_FIRST_BLOCK_PART_1;
end else begin
nextstate = MEMWRITE_UNALIGNED;
end
end
GEN_FIRST_BLOCK_PART_1: nextstate = GEN_FIRST_BLOCK_PART_2;
GEN_FIRST_BLOCK_PART_2: begin
if((func3 == 3'b000 && ~(&last_bits_saved_address)) ||
Expand Down Expand Up @@ -230,33 +269,49 @@ always @(*) begin
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3: nextstate = MERGE_WRITE_VALUE_1;
MERGE_WRITE_VALUE_1: nextstate = WRITE_VALUE_1;
WRITE_VALUE_1: begin
if(func3 == 3'b010 || (func3 == 3'b001 && last_bits_saved_address == 2'b11)) begin
nextstate = CALC_SECOND_BLOCK_ADDRESS_TO_WRITE;
if(memory_response) begin
if(func3 == 3'b010 || (func3 == 3'b001 && last_bits_saved_address == 2'b11)) begin
nextstate = CALC_SECOND_BLOCK_ADDRESS_TO_WRITE;
end else begin
nextstate = FETCH;
end
end else begin
nextstate = FETCH;
nextstate = WRITE_VALUE_1;
end
end
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE: nextstate = READ_SECOND_BLOCK_TO_WRITE;
READ_SECOND_BLOCK_TO_WRITE: nextstate = LOAD_SECOND_BLOCK_TO_WRITE;
READ_SECOND_BLOCK_TO_WRITE: begin
if(memory_response) begin
nextstate = LOAD_SECOND_BLOCK_TO_WRITE;
end else begin
nextstate = READ_SECOND_BLOCK_TO_WRITE;
end
end
LOAD_SECOND_BLOCK_TO_WRITE: nextstate = LOAD_SECOND_BLOCK_TO_WRITE_2;
LOAD_SECOND_BLOCK_TO_WRITE_2: nextstate = SWAP_VALUE_DIRECTION_2;
SWAP_VALUE_DIRECTION_2: nextstate = CLEAR_VALUE_PART_2;
CLEAR_VALUE_PART_2: nextstate = CLEAR_VALUE_PART_2_1;
CLEAR_VALUE_PART_2_1: nextstate = MERGE_WRITE_VALUE_2;
MERGE_WRITE_VALUE_2: nextstate = WRITE_VALUE_2;
WRITE_VALUE_2: nextstate = FETCH;
WRITE_VALUE_2: begin
if(memory_response) begin
nextstate = FETCH;
end else begin
nextstate = WRITE_VALUE_2;
end
end
default: nextstate = FETCH;
endcase
end

always @(*) begin
pc_write_cond <= 1'b0;
pc_write <= 1'b0;
//pc_write <= 1'b0;
//ir_write <= 1'b0;
lorD <= 2'b00;
memory_read <= 1'b0;
memory_write <= 1'b0;
memory_to_reg <= 3'b000;
ir_write <= 1'b0;
pc_source <= 1'b0;
aluop <= 2'b00;
alu_src_b <= 3'b000;
Expand All @@ -272,13 +327,14 @@ always @(*) begin
save_value <= 1'b0;
save_value_2 <= 1'b0;
write_data_in <= 1'b0;
save_write_value <= 1'b0;

case (state)
FETCH: begin
memory_read <= 1'b1;
ir_write <= 1'b1;
alu_src_b <= 3'b001;
pc_write <= 1'b1;
//ir_write <= 1'b1;
//pc_write <= 1'b1;
end

DECODE: begin
Expand All @@ -289,18 +345,18 @@ always @(*) begin
MEMADR: begin
alu_src_a <= 3'b001;
alu_src_b <= 3'b010;
save_address <= 1'b1;
end

MEMREAD: begin
memory_read <= 1'b1;
lorD <= 2'b01;
lorD <= 2'b10;
end

MEMREAD_UNALIGNED: begin
control_memory_op <= 1'b1;
memory_read <= 1'b1;
lorD <= 2'b01;
save_address <= 1'b1;
lorD <= 2'b10;
end

MEMWB: begin
Expand All @@ -321,13 +377,14 @@ always @(*) begin
end

CALC_NEXT_ADDRESS: begin
save_address <= 1'b1;
alu_src_a <= 3'b110;
alu_src_b <= 3'b001;
end

READ_SECOND_BLOCK: begin
memory_read <= 1'b1;
lorD <= 2'b01;
lorD <= 2'b10;
control_memory_op <= 1'b1;
end

Expand All @@ -345,14 +402,13 @@ always @(*) begin

MEMWRITE: begin
memory_write <= 1'b1;
lorD <= 2'b01;
lorD <= 2'b10;
end

MEMWRITE_UNALIGNED: begin
control_memory_op <= 1'b1;
memory_read <= 1'b1;
lorD <= 2'b01;
save_address <= 1'b1;
lorD <= 2'b10;
end

GEN_FIRST_BLOCK_PART_1: begin
Expand Down Expand Up @@ -428,6 +484,7 @@ always @(*) begin
MERGE_WRITE_VALUE_1: begin
alu_src_a <= 3'b101;
alu_src_b <= 3'b110;
save_write_value <= 1'b1;
end

WRITE_VALUE_1: begin
Expand All @@ -440,12 +497,12 @@ always @(*) begin
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE: begin
alu_src_a <= 3'b110;
alu_src_b <= 3'b001;
save_address <= 1'b1;
end

READ_SECOND_BLOCK_TO_WRITE: begin
save_address <= 1'b1;
memory_read <= 1'b1;
lorD <= 2'b01;
lorD <= 2'b10;
control_memory_op <= 1'b1;
end

Expand Down Expand Up @@ -484,6 +541,7 @@ always @(*) begin
end

MERGE_WRITE_VALUE_2: begin
save_write_value <= 1'b1;
alu_src_a <= 3'b101;
alu_src_b <= 3'b110;
end
Expand Down
39 changes: 25 additions & 14 deletions src/core/core.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,11 @@ module Core #(
) (
// Control signal
input wire clk,
input wire halt,
input wire reset,

// Memory BUS
input wire memory_response,
output wire memory_read,
output wire memory_write,
output wire [2:0] option,
Expand Down Expand Up @@ -48,7 +50,7 @@ module Core #(
wire IRWrite, zero, reg_write, pc_load, and_zero_out,
pc_write_cond, pc_write, is_immediate, csr_write_enable,
alu_input_selector, save_address, control_memory_op,
save_value, save_value_2, write_data_in;
save_value, save_value_2, write_data_in, save_write_value;
wire [1:0] aluop, lorD;
wire [2:0] alu_src_a, alu_src_b, memory_to_reg, control_unit_memory_op;
wire [3:0] aluop_out, control_unit_aluop;
Expand All @@ -57,10 +59,10 @@ wire [31:0] pc_output, pc_input, register_input,
register_data_1_out, register_data_2_out,
csr_data_out, register_data_RD_out;
reg [31:0] instruction_register, memory_register, alu_out_register,
register_data_1, register_data_2, pc_old, temp_reg1, temp_reg2,
temp_reg3;
register_data_1, register_data_2, pc_old, temp_address, temp_reg2,
temp_reg3, temp_write_value;

assign write_data = (write_data_in == 1'b1) ? alu_out_register : register_data_2_out;
assign write_data = (write_data_in == 1'b1) ? temp_write_value : register_data_2_out;
assign option = (lorD == 2'b00 | control_memory_op == 1'b1)
? control_unit_memory_op : instruction_register[14:12];

Expand All @@ -71,8 +73,9 @@ initial begin
register_data_2 = 32'h00000000;
alu_out_register = 32'h00000000;
pc_old = 32'h00000000;
temp_reg1 = 32'h00000000;
temp_address = 32'h00000000;
temp_reg2 = 32'h00000000;
temp_write_value = 32'h00000000;
end

PC Pc(
Expand All @@ -87,7 +90,7 @@ MUX MemoryAddressMUX(
.option({1'b0, lorD}),
.A(pc_output),
.B(alu_out_register),
.C(temp_reg1),
.C(temp_address),
.D(0),
.E(0),
.F(0),
Expand Down Expand Up @@ -117,7 +120,7 @@ MUX AluInputAMUX(
.D(32'd0),
.E(memory_register),
.F(alu_out_register),
.G(temp_reg1),
.G(temp_address),
.H(temp_reg2),
.S(alu_input_a)
);
Expand All @@ -128,10 +131,10 @@ MUX AluInputBMUX(
.B(32'd4),
.C(immediate),
.D(register_data_RD_out),
.E({27'h00000, temp_reg1[1:0], 3'h0}),
.F({26'h00000, 3'b100 - temp_reg1[1:0], 3'h0}),
.E({27'h00000, temp_address[1:0], 3'h0}),
.F({26'h00000, 3'b100 - temp_address[1:0], 3'h0}),
.G(temp_reg3),
.H({27'h00000, temp_reg1[1:0] + 1'b1, 3'h0}),
.H({27'h00000, temp_address[1:0] + 1'b1, 3'h0}),
.S(alu_input_b)
);

Expand Down Expand Up @@ -168,7 +171,7 @@ Control_Unit Control_Unit(
.clk(clk),
.reset(reset),
.last_bits(alu_out[1:0]),
.last_bits_saved_address(temp_reg1[1:0]),
.last_bits_saved_address(temp_address[1:0]),
.func3(instruction_register[14:12]),
.instruction_opcode(instruction_register[6:0]),
.pc_write_cond(pc_write_cond),
Expand All @@ -192,7 +195,9 @@ Control_Unit Control_Unit(
.control_memory_op(control_memory_op),
.save_value(save_value),
.save_value_2(save_value_2),
.write_data_in(write_data_in)
.write_data_in(write_data_in),
.memory_response(memory_response),
.save_write_value(save_write_value)
);

ALU_Control ALU_Control(
Expand Down Expand Up @@ -244,22 +249,28 @@ always @(posedge clk ) begin
register_data_2 <= 32'h00000000;
alu_out_register <= 32'h00000000;
pc_old <= 32'h00000000;
temp_reg1 <= 32'h00000000;
temp_address <= 32'h00000000;
temp_reg2 <= 32'h00000000;
temp_reg3 <= 32'h00000000;
temp_write_value <= 32'h00000000;
end else begin
if(IRWrite == 1'b1)begin
instruction_register <= read_data;
pc_old <= pc_output;
end
if(save_address == 1'b1) begin
temp_reg1 <= alu_out_register;
temp_address <= alu_out;
end
if(save_value == 1'b1) begin
temp_reg2 <= memory_register;
end
if(save_value_2 == 1'b1) begin
temp_reg3 <= alu_out_register;
end
if(save_write_value) begin
temp_write_value <= alu_out;
end

memory_register <= read_data;
register_data_1 <= register_data_1_out;
register_data_2 <= register_data_2_out;
Expand Down
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