feat: add nextSource in cache IO

IntelLabs · Jan 10, 2025 · d9f91c4 · d9f91c4
1 parent b08c17e
commit d9f91c4
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diff --git a/src/main/scala/grapecoveDcache/DCache.scala b/src/main/scala/grapecoveDcache/DCache.scala
@@ -572,6 +572,7 @@ class GPCDCacheImp(outer: BaseDCache) extends BaseDCacheImp(outer) {
 
   // return resp
   io.nextCycleWb := mshrs.io.nextCycleWb
+  io.nextSource  := mshrs.io.nextSourceId
   io.resp.valid  := s1_cacheResp.valid | mshrsResp.valid
   io.resp.bits   := Mux(s1_cacheResp.valid, s1_cacheResp.bits, mshrsResp.bits)
 

diff --git a/src/main/scala/grapecoveDcache/DataExchangeIO.scala b/src/main/scala/grapecoveDcache/DataExchangeIO.scala
@@ -38,6 +38,7 @@ class DataExchangeIO extends Bundle {
   val req         = Flipped(Decoupled(new DataExchangeReq))
   val resp        = Valid(new DataExchangeResp)
   val nextCycleWb = Bool() // next cycle occupy wb stage
+  val nextSource  = UInt(MasterSource.width.W)
   val fenceRdy    = Bool()
   val s1_kill     = Input(Bool())
 }