fix: probeQueue

1. probePerm width from bdWidth to cWidth 2. remove useless assertion
IntelLabs · Jan 14, 2025 · b7c185a · b7c185a
1 parent 81e2d39
commit b7c185a
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Showing 2 changed files with 6 additions and 7 deletions.
diff --git a/src/main/scala/grapecoveDcache/MSHRIO.scala b/src/main/scala/grapecoveDcache/MSHRIO.scala
@@ -36,7 +36,7 @@ class MSHREntryIO extends Bundle() {
   // probe permission
   val probeValid         = Input(Bool())
   val probeLineAddrMatch = Output(Bool())
-  val probePermission    = Input(UInt(TLPermissions.bdWidth.W))
+  val probePermission    = Input(UInt(TLPermissions.cWidth.W))
   val probeState         = Output(UInt(ProbeMSHRState.width.W))
 }
 
@@ -127,7 +127,7 @@ class RefillMSHRFile extends Bundle() {
 
 class ProbeMSHRFile extends Bundle() {
   val valid           = Input(Bool())
-  val probePermission = Input(UInt(TLPermissions.bdWidth.W))
+  val probePermission = Input(UInt(TLPermissions.cWidth.W))
   val lineAddr        = Input(UInt(lineAddrWidth.W))
 
   val pass     = Output(Bool())

diff --git a/src/main/scala/grapecoveDcache/ProbeQueue.scala b/src/main/scala/grapecoveDcache/ProbeQueue.scala
@@ -92,9 +92,8 @@ class ProbeQueue(
   io.wbReq.bits.data      := DontCare // FIXME
   io.wbReq.bits.hasData   := false.B
 
-  io.memProbe.ready := (state === s_invalid) &&
-    (!io.lrscAddr.valid ||
-      io.lrscAddr.bits =/= getLineAddr(io.memProbe.bits.address))
-
-  assert(io.memProbe.bits.opcode === TLMessages.Probe || ~io.memProbe.valid)
+  io.memProbe.ready :=
+    (state === s_invalid) &&
+      (!io.lrscAddr.valid ||
+        io.lrscAddr.bits =/= getLineAddr(io.memProbe.bits.address))
 }