Merge pull request sysprog21#535 from eleanorLYJ/improve-build-tests

Fix build failures and expand test coverage

.github/workflows/main.yml

@@ -36,6 +36,10 @@ jobs:
   host-x64:
     needs: [detect-code-related-file-changes]
     if: needs.detect-code-related-file-changes.outputs.has_code_related_changes == 'true'
+    strategy:
+      fail-fast: false
+      matrix:
+        compiler: [gcc, clang]
     runs-on: ubuntu-24.04
     steps:
     - uses: actions/checkout@v4
@@ -49,47 +53,95 @@ jobs:
             sudo chmod +x ./llvm.sh
             sudo ./llvm.sh 18
       shell: bash
+    - name: Install compiler
+      id: install_cc
+      uses: rlalik/setup-cpp-compiler@master
+      with:
+        compiler: ${{ matrix.compiler }}
     - name: default build
+      env:
+        CC: ${{ steps.install_cc.outputs.cc }}
       run: make -j$(nproc)
+      if: ${{ always() }}
     - name: check + tests
+      env:
+        CC: ${{ steps.install_cc.outputs.cc }}
       run: |
+            make clean
             make check -j$(nproc)
             make tests -j$(nproc)
             make misalign -j$(nproc)
             make tool -j$(nproc)
+      if: ${{ always() }}
     - name: diverse configurations
+      env:
+        CC: ${{ steps.install_cc.outputs.cc }}
       run: |
             make distclean && make ENABLE_EXT_M=0 check -j$(nproc)
             make distclean && make ENABLE_EXT_A=0 check -j$(nproc)
             make distclean && make ENABLE_EXT_F=0 check -j$(nproc)
             make distclean && make ENABLE_EXT_C=0 check -j$(nproc)
             make distclean && make ENABLE_SDL=0 check -j$(nproc)
+            make distclean && make ENABLE_Zicsr=0 check -j$(nproc)
+            make distclean && make ENABLE_MOP_FUSION=0 check -j$(nproc)
+            make distclean && make ENABLE_BLOCK_CHAINING=0 check -j$(nproc)
+            make distclean && make ENABLE_Zba=0 check -j$(nproc)
+            make distclean && make ENABLE_Zbb=0 check -j$(nproc)
+            make distclean && make ENABLE_Zbc=0 check -j$(nproc)
+            make distclean && make ENABLE_Zbs=0 check -j$(nproc)
+            make distclean && make ENABLE_Zifencei=0 check -j$(nproc)
+      if: ${{ always() }}
     - name: misalignment test in block emulation
+      env:
+        CC: ${{ steps.install_cc.outputs.cc }}
       run: |
             make -C tests/system/alignment/
             make distclean && make ENABLE_ELF_LOADER=1 ENABLE_EXT_C=0 ENABLE_SYSTEM=1 misalign-in-blk-emu -j$(nproc)
+      if: ${{ always() }}
     - name: MMU test
+      env:
+        CC: ${{ steps.install_cc.outputs.cc }}
       run: |
             make -C tests/system/mmu/
             make distclean && make ENABLE_ELF_LOADER=1 ENABLE_SYSTEM=1 mmu-test -j$(nproc)
+      if: ${{ always() }}
     - name: gdbstub test
+      env:
+        CC: ${{ steps.install_cc.outputs.cc }}
       run: |
             make distclean && make ENABLE_GDBSTUB=1 gdbstub-test -j$(nproc)
+      if: ${{ always() }}
     - name: JIT test
+      env:
+        CC: ${{ steps.install_cc.outputs.cc }}
       run: |
             make ENABLE_JIT=1 clean && make ENABLE_JIT=1 check -j$(nproc)
             make ENABLE_JIT=1 clean && make ENABLE_EXT_A=0 ENABLE_JIT=1 check -j$(nproc)
             make ENABLE_JIT=1 clean && make ENABLE_EXT_F=0 ENABLE_JIT=1 check -j$(nproc)
             make ENABLE_JIT=1 clean && make ENABLE_EXT_C=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_EXT_M=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_Zba=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_Zbb=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_Zbc=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_Zbs=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_Zicsr=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_Zifencei=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_MOP_FUSION=0 ENABLE_JIT=1 check -j$(nproc)
+            make ENABLE_JIT=1 clean && make ENABLE_BLOCK_CHAINING=0 ENABLE_JIT=1 check -j$(nproc)
+      if: ${{ always() }}
     - name: undefined behavior test
       run: |
             make clean && make ENABLE_UBSAN=1 check -j$(nproc)
             make ENABLE_JIT=1 clean && make ENABLE_JIT=1 ENABLE_UBSAN=1 check -j$(nproc)
+      if: ${{ always() }}
     - name: boot Linux kernel test
+      env:
+        CC: ${{ steps.install_cc.outputs.cc }}
       run: |
             make clean && make ENABLE_SYSTEM=1 && make ENABLE_SYSTEM=1 artifact -j$(nproc)
             .ci/boot-linux.sh
             make ENABLE_SYSTEM=1 clean
+      if: ${{ always() }}
 
   host-arm64:
     needs: [detect-code-related-file-changes]

Makefile

@@ -7,7 +7,7 @@ BIN := $(OUT)/rv32emu
 CONFIG_FILE := $(OUT)/.config
 -include $(CONFIG_FILE)
 
-CFLAGS = -std=gnu99 -O2 -Wall -Wextra
+CFLAGS = -std=gnu99 -O2 -Wall -Wextra -Werror
 CFLAGS += -Wno-unused-label
 CFLAGS += -include src/common.h -Isrc/
 

mk/tests.mk

@@ -83,7 +83,7 @@ $(CACHE_TEST_OUT): $(CACHE_TEST_TARGET)
 
 $(CACHE_TEST_TARGET): $(CACHE_TEST_OBJS)
 	$(VECHO) "  CC\t$@\n"
-	$(Q)$(CC) $^ -o $@
+	$(Q)$(CC) $^ -o $@ $(LDFLAGS)
 
 $(CACHE_TEST_OUTDIR)/%.o: $(CACHE_TEST_SRCDIR)/%.c
 	$(VECHO) "  CC\t$@\n"
@@ -95,7 +95,7 @@ $(MAP_TEST_OUT): $(MAP_TEST_TARGET)
 
 $(MAP_TEST_TARGET): $(MAP_TEST_OBJS)
 	$(VECHO) "  CC\t$@\n"
-	$(Q)$(CC) $^ -o $@
+	$(Q)$(CC) $^ -o $@ $(LDFLAGS)
 
 $(MAP_TEST_OUTDIR)/%.o: $(MAP_TEST_SRCDIR)/%.c
 	$(VECHO) "  CC\t$@\n"
@@ -107,7 +107,7 @@ $(PATH_TEST_OUT): $(PATH_TEST_TARGET)
 
 $(PATH_TEST_TARGET): $(PATH_TEST_OBJS)
 	$(VECHO) "  CC\t$@\n"
-	$(Q)$(CC) $^ -o $@
+	$(Q)$(CC) $^ -o $@ $(LDFLAGS)
 
 $(PATH_TEST_OUTDIR)/%.o: $(PATH_TEST_SRCDIR)/%.c
 	$(VECHO) "  CC\t$@\n"

src/emulate.c

@@ -42,7 +42,9 @@ extern struct target_ops gdbstub_ops;
 #define IF_imm(i, v) (i->imm == v)
 
 #if RV32_HAS(SYSTEM)
+#if !RV32_HAS(JIT)
 static bool need_clear_block_map = false;
+#endif
 static uint32_t reloc_enable_mmu_jalr_addr;
 static bool reloc_enable_mmu = false;
 bool need_retranslate = false;
@@ -79,14 +81,14 @@ static void __trap_handler(riscv_t *rv);
     }
 
 /* FIXME: use more precise methods for updating time, e.g., RTC */
+#if RV32_HAS(Zicsr)
 static uint64_t ctr = 0;
 static inline void update_time(riscv_t *rv)
 {
     rv->csr_time[0] = ctr & 0xFFFFFFFF;
     rv->csr_time[1] = ctr >> 32;
 }
 
-#if RV32_HAS(Zicsr)
 /* get a pointer to a CSR */
 static uint32_t *csr_get_ptr(riscv_t *rv, uint32_t csr)
 {
@@ -374,42 +376,45 @@ static uint32_t peripheral_update_ctr = 64;
 #endif
 
 /* Interpreter-based execution path */
-#define RVOP(inst, code, asm)                                         \
-    static bool do_##inst(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, \
-                          uint32_t PC)                                \
-    {                                                                 \
-        IIF(RV32_HAS(SYSTEM))(ctr++;, ) cycle++;                      \
-        code;                                                         \
-        IIF(RV32_HAS(SYSTEM))                                         \
-        (                                                             \
-            if (need_handle_signal) {                                 \
-                need_handle_signal = false;                           \
-                return true;                                          \
-            }, ) nextop : PC += __rv_insn_##inst##_len;               \
-        IIF(RV32_HAS(SYSTEM))                                         \
-        (IIF(RV32_HAS(JIT))(                                          \
-             , if (unlikely(need_clear_block_map)) {                  \
-                 block_map_clear(rv);                                 \
-                 need_clear_block_map = false;                        \
-                 rv->csr_cycle = cycle;                               \
-                 rv->PC = PC;                                         \
-                 return false;                                        \
-             }), );                                                   \
-        if (unlikely(RVOP_NO_NEXT(ir)))                               \
-            goto end_op;                                              \
-        const rv_insn_t *next = ir->next;                             \
-        MUST_TAIL return next->impl(rv, next, cycle, PC);             \
-    end_op:                                                           \
-        rv->csr_cycle = cycle;                                        \
-        rv->PC = PC;                                                  \
-        return true;                                                  \
+#define RVOP(inst, code, asm)                                               \
+    static bool do_##inst(riscv_t *rv, const rv_insn_t *ir, uint64_t cycle, \
+                          uint32_t PC)                                      \
+    {                                                                       \
+        IIF(RV32_HAS(SYSTEM))(ctr++;, ) cycle++;                            \
+        code;                                                               \
+        IIF(RV32_HAS(SYSTEM))                                               \
+        (                                                                   \
+            if (need_handle_signal) {                                       \
+                need_handle_signal = false;                                 \
+                return true;                                                \
+            }, ) nextop : PC += __rv_insn_##inst##_len;                     \
+        IIF(RV32_HAS(SYSTEM))                                               \
+        (IIF(RV32_HAS(JIT))(                                                \
+             , if (unlikely(need_clear_block_map)) {                        \
+                 block_map_clear(rv);                                       \
+                 need_clear_block_map = false;                              \
+                 rv->csr_cycle = cycle;                                     \
+                 rv->PC = PC;                                               \
+                 return false;                                              \
+             }), );                                                         \
+        if (unlikely(RVOP_NO_NEXT(ir)))                                     \
+            goto end_op;                                                    \
+        const rv_insn_t *next = ir->next;                                   \
+        MUST_TAIL return next->impl(rv, next, cycle, PC);                   \
+    end_op:                                                                 \
+        rv->csr_cycle = cycle;                                              \
+        rv->PC = PC;                                                        \
+        return true;                                                        \
     }
 
 #include "rv32_template.c"
 #undef RVOP
 
 /* multiple LUI */
-static bool do_fuse1(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
+static bool do_fuse1(riscv_t *rv,
+                     const rv_insn_t *ir,
+                     uint64_t cycle,
+                     uint32_t PC)
 {
     cycle += ir->imm2;
     opcode_fuse_t *fuse = ir->fuse;
@@ -426,7 +431,10 @@ static bool do_fuse1(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
 }
 
 /* LUI + ADD */
-static bool do_fuse2(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
+static bool do_fuse2(riscv_t *rv,
+                     const rv_insn_t *ir,
+                     uint64_t cycle,
+                     uint32_t PC)
 {
     cycle += 2;
     rv->X[ir->rd] = ir->imm;
@@ -442,7 +450,10 @@ static bool do_fuse2(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
 }
 
 /* multiple SW */
-static bool do_fuse3(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
+static bool do_fuse3(riscv_t *rv,
+                     const rv_insn_t *ir,
+                     uint64_t cycle,
+                     uint32_t PC)
 {
     cycle += ir->imm2;
     opcode_fuse_t *fuse = ir->fuse;
@@ -466,7 +477,10 @@ static bool do_fuse3(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
 }
 
 /* multiple LW */
-static bool do_fuse4(riscv_t *rv, rv_insn_t *ir, uint64_t cycle, uint32_t PC)
+static bool do_fuse4(riscv_t *rv,
+                     const rv_insn_t *ir,
+                     uint64_t cycle,
+                     uint32_t PC)
 {
     cycle += ir->imm2;
     opcode_fuse_t *fuse = ir->fuse;
@@ -550,6 +564,7 @@ FORCE_INLINE bool insn_is_translatable(uint8_t opcode)
 }
 #endif
 
+#if RV32_HAS(BLOCK_CHAINING)
 FORCE_INLINE bool insn_is_unconditional_branch(uint8_t opcode)
 {
     switch (opcode) {
@@ -558,7 +573,9 @@ FORCE_INLINE bool insn_is_unconditional_branch(uint8_t opcode)
     case rv_insn_jal:
     case rv_insn_jalr:
     case rv_insn_mret:
+#if RV32_HAS(Zicsr)
     case rv_insn_csrrw:
+#endif
 #if RV32_HAS(SYSTEM)
     case rv_insn_sret:
 #endif
@@ -588,6 +605,7 @@ FORCE_INLINE bool insn_is_direct_branch(uint8_t opcode)
         return false;
     }
 }
+#endif
 
 FORCE_INLINE bool insn_is_indirect_branch(uint8_t opcode)
 {
@@ -664,6 +682,7 @@ static void block_translate(riscv_t *rv, block_t *block)
     block->ir_tail->next = NULL;
 }
 
+#if RV32_HAS(MOP_FUSION)
 #define COMBINE_MEM_OPS(RW)                                       \
     next_ir = ir->next;                                           \
     count = 1;                                                    \
@@ -800,6 +819,7 @@ static void match_pattern(riscv_t *rv, block_t *block)
         }
     }
 }
+#endif
 
 typedef struct {
     bool is_constant[N_RV_REGS];

src/jit.c

@@ -725,6 +725,7 @@ static inline void emit_alu64(struct jit_state *state, int op, int src, int dst)
 #endif
 }
 
+#if RV32_HAS(EXT_M)
 static inline void emit_alu64_imm8(struct jit_state *state,
                                    int op,
                                    int src UNUSED,
@@ -742,6 +743,7 @@ static inline void emit_alu64_imm8(struct jit_state *state,
     }
 #endif
 }
+#endif
 
 /* Register to register mov */
 static inline void emit_mov(struct jit_state *state, int src, int dst)
@@ -1690,6 +1692,7 @@ static void ra_load2(struct jit_state *state, int vm_reg_idx1, int vm_reg_idx2)
                   offsetof(riscv_t, X) + 4 * vm_reg_idx2);
 }
 
+#if RV32_HAS(EXT_M)
 static void ra_load2_sext(struct jit_state *state,
                           int vm_reg_idx1,
                           int vm_reg_idx2,
@@ -1733,6 +1736,7 @@ static void ra_load2_sext(struct jit_state *state,
                       offsetof(riscv_t, X) + 4 * vm_reg_idx2);
     }
 }
+#endif
 
 void parse_branch_history_table(struct jit_state *state, rv_insn_t *ir)
 {

src/riscv.c

@@ -621,8 +621,10 @@ bool rv_has_halted(riscv_t *rv)
 void rv_delete(riscv_t *rv)
 {
     assert(rv);
-#if !RV32_HAS(JIT)
+#if !RV32_HAS(JIT) || (RV32_HAS(SYSTEM) && !RV32_HAS(ELF_LOADER))
     vm_attr_t *attr = PRIV(rv);
+#endif
+#if !RV32_HAS(JIT)
     map_delete(attr->fd_map);
     memory_delete(attr->mem);
     block_map_destroy(rv);

src/t2c.c

@@ -74,8 +74,10 @@ FORCE_INLINE LLVMBasicBlockRef t2c_block_map_search(struct LLVM_block_map *map,
 T2C_LLVM_GEN_ADDR(rs1, X, ir->rs1);
 T2C_LLVM_GEN_ADDR(rs2, X, ir->rs2);
 T2C_LLVM_GEN_ADDR(rd, X, ir->rd);
+#if RV32_HAS(EXT_C)
 T2C_LLVM_GEN_ADDR(ra, X, rv_reg_ra);
 T2C_LLVM_GEN_ADDR(sp, X, rv_reg_sp);
+#endif
 T2C_LLVM_GEN_ADDR(PC, PC, 0);
 
 #define T2C_LLVM_GEN_STORE_IMM32(builder, val, addr) \