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Small patch up for AT32F415 #416

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merged 4 commits into from
Jan 10, 2025
Merged

Small patch up for AT32F415 #416

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5f9c615
Enable advanced DMA check when using DMAMUX and GPIO changes
HorrorTroll Jan 9, 2025
c8fb8a4
Deleted TMR10/11 for ICU driver due to only 1 channel available
HorrorTroll Jan 10, 2025
9a3a5f7
Remove duplicate multiplexing function and update OTG LLD driver
HorrorTroll Jan 10, 2025
6c6ebb9
Removed TMR alias for ISR and update CMSIS version
HorrorTroll Jan 10, 2025
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2 changes: 0 additions & 2 deletions demos/AT32/RT-AT-START-F415/cfg/mcuconf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -151,8 +151,6 @@
#define AT32_ICU_USE_TMR4 FALSE
#define AT32_ICU_USE_TMR5 FALSE
#define AT32_ICU_USE_TMR9 FALSE
#define AT32_ICU_USE_TMR10 FALSE
#define AT32_ICU_USE_TMR11 FALSE

/*
* PWM driver system settings.
Expand Down
22 changes: 5 additions & 17 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
**************************************************************************
* @file at32f415cx.h
* @author Artery Technology & HorrorTroll & Zhaqian
* @version v2.1.4
* @date 01-February-2024
* @version v2.1.6
* @date 13-December-2024
* @brief AT32F415Cx header file.
*
**************************************************************************
Expand Down Expand Up @@ -42,11 +42,11 @@
#endif

/**
* @brief CMSIS Device version number V2.1.4
* @brief CMSIS Device version number V2.1.6
*/
#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x06) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\
|(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\
Expand Down Expand Up @@ -3019,7 +3019,7 @@ typedef struct
#define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */

#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos)
#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */

Expand Down Expand Up @@ -3266,9 +3266,6 @@ typedef struct
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */

#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */
Expand All @@ -3284,9 +3281,6 @@ typedef struct
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */

#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */
Expand All @@ -3302,9 +3296,6 @@ typedef struct
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */

#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */
Expand All @@ -3320,9 +3311,6 @@ typedef struct
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */

#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */
Expand Down
22 changes: 5 additions & 17 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
**************************************************************************
* @file at32f415kx.h
* @author Artery Technology & HorrorTroll & Zhaqian
* @version v2.1.4
* @date 01-February-2024
* @version v2.1.6
* @date 13-December-2024
* @brief AT32F415Kx header file.
*
**************************************************************************
Expand Down Expand Up @@ -42,11 +42,11 @@
#endif

/**
* @brief CMSIS Device version number V2.1.4
* @brief CMSIS Device version number V2.1.6
*/
#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x06) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\
|(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\
Expand Down Expand Up @@ -2995,7 +2995,7 @@ typedef struct
#define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */

#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos)
#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */

Expand Down Expand Up @@ -3225,9 +3225,6 @@ typedef struct
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */

#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */
Expand All @@ -3243,9 +3240,6 @@ typedef struct
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */

#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */
Expand All @@ -3261,9 +3255,6 @@ typedef struct
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */

#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */
Expand All @@ -3279,9 +3270,6 @@ typedef struct
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */

#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */
Expand Down
22 changes: 5 additions & 17 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
**************************************************************************
* @file at32f415rx.h
* @author Artery Technology & HorrorTroll & Zhaqian
* @version v2.1.4
* @date 01-February-2024
* @version v2.1.6
* @date 13-December-2024
* @brief AT32F415Rx header file.
*
**************************************************************************
Expand Down Expand Up @@ -42,11 +42,11 @@
#endif

/**
* @brief CMSIS Device version number V2.1.4
* @brief CMSIS Device version number V2.1.6
*/
#define __AT32F415_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F415_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_MINOR (0x06) /*!< [15:8] minor version */
#define __AT32F415_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F415_LIBRARY_VERSION ((__AT32F415_LIBRARY_VERSION_MAJOR << 24)\
|(__AT32F415_LIBRARY_VERSION_MIDDLE << 16)\
Expand Down Expand Up @@ -3037,7 +3037,7 @@ typedef struct
#define IOMUX_REMAP3_TMR11_GMUX_3 (0x8U << IOMUX_REMAP3_TMR11_GMUX_Pos) /*!< 0x00000800 */

#define IOMUX_REMAP3_TMR11_GMUX_MUX0 0x00000000U /*!< CH1/PB9 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000002 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos (9U) /*!< 0x00000200 */
#define IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP3_TMR11_GMUX_MUX2_Pos)
#define IOMUX_REMAP3_TMR11_GMUX_MUX2 IOMUX_REMAP3_TMR11_GMUX_MUX2_Msk /*!< CH1/PA7 */

Expand Down Expand Up @@ -3298,9 +3298,6 @@ typedef struct
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_Pos) /*!< 0x00000002 */

#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos (0U) /*!< 0x00000001 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 BRK channel 1 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos (1U) /*!< 0x00000002 */
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_BK1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 BRK channel 1 */
Expand All @@ -3316,9 +3313,6 @@ typedef struct
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_Pos) /*!< 0x00000008 */

#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos (2U) /*!< 0x00000004 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX1_Msk /*!< TMR1_GMUX IO signal is connected to TMR1 channel 1 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos (3U) /*!< 0x00000008 */
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR1_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR1 channel 1 */
Expand All @@ -3334,9 +3328,6 @@ typedef struct
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_Pos) /*!< 0x00000020 */

#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX0 0x00000000U /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos (4U) /*!< 0x00000010 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX1_Msk /*!< TMR2_GMUX IO signal is connected to TMR2 channel 4 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos (5U) /*!< 0x00000020 */
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR2_CH4_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR2 channel 4 */
Expand All @@ -3352,9 +3343,6 @@ typedef struct
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_1 (0x2U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_Pos) /*!< 0x00000080 */

#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX0 0x00000000U /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos (6U) /*!< 0x00000040 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Pos)
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX1_Msk /*!< TMR3_GMUX IO signal is connected to TMR3 channel 1 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos (7U) /*!< 0x00000080 */
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk (0x1U << IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Pos)
#define IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2 IOMUX_REMAP8_TMR3_CH1_CMP_GMUX_MUX2_Msk /*!< CMP output signal is connected to TMR3 channel 1 */
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9 changes: 0 additions & 9 deletions os/hal/ports/AT32/AT32F415/at32_isr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -210,15 +210,6 @@
#define AT32_TMR4_NUMBER 30
#define AT32_TMR5_NUMBER 50

/* Aliases.*/
#define AT32_TMR9_HANDLER VectorA0
#define AT32_TMR10_HANDLER VectorA4
#define AT32_TMR11_HANDLER VectorA8

#define AT32_TMR9_NUMBER 24
#define AT32_TMR10_NUMBER 25
#define AT32_TMR11_NUMBER 26

/*
* USART units.
*/
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