🎉 Added more displays & reset along with reset & enable controls (#14)

* ✨ Added LEDs indicators * 🚀 Updated DisplayDecoder * 💥 Added extra hex display & leds with reset & enable * ✨ Added reset & enable for encrypt & decrypt modules * ⚡ Fixed main module * added enable led --------- Co-authored-by: Ahmed Amr <[email protected]>
AhmedSobhy01 · May 13, 2024 · fb46326 · fb46326
1 parent 234c797
commit fb46326
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Showing 4 changed files with 122 additions and 79 deletions.
diff --git a/AES.v b/AES.v
@@ -1,11 +1,18 @@
-module AES(LED, HEX0, HEX1, HEX2, sel, clk);
+module AES(LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, sel, clk, reset, enable);
     input [1:0] sel; // 00 -> 128-bit AES, 01 -> 192-bit AES, 10/11 -> 256-bit AES
     input clk;
+    input reset;
+    input enable;
 
-    output LED;
-    output [6:0] HEX0;
-    output [6:0] HEX1;
-    output [6:0] HEX2;
+    output [9:0] LEDR; // 0 -> Encryption Success, 1 -> Decryption Success, 5 -> 128-bit AES, 6 -> 192-bit AES, 7 -> 256-bit AES, 9 -> Reset
+
+    output [6:0] HEX0; // First bit of state (LSB)
+    output [6:0] HEX1; // Second bit of state
+    output [6:0] HEX2; // Third bit of state
+
+    output [6:0] HEX3; // First hexadecimal digit of state (LSB)
+    output [6:0] HEX4; // Second hexadecimal digit of state
+    output [6:0] HEX5; // Third hexadecimal digit of state
 
     // Keys
     wire [127:0] key128 = 128'h000102030405060708090a0b0c0d0e0f;
@@ -28,34 +35,34 @@ module AES(LED, HEX0, HEX1, HEX2, sel, clk);
     reg [1:0] selReg = 0;
 
     // 128-bit AES
-    wire aesReset128 = selReg == 0 ? 1'b0 : 1'b1;
+    wire aesReset128 = (reset || selReg != 0) ? 1'b1 : 1'b0;
     wire [127:0] tempEncryptedOutput128;
     wire [127:0] tempDecryptedOutput128;
     wire [1407:0] allKeys128;
 
     KeyExpansion #(4, 10) keysGetter128(key128, allKeys128);
-    AESEncrypt #(4, 10) aese128(data, allKeys128, tempEncryptedOutput128, clk, aesReset128);
-    AESDecrypt #(4, 10) aesd128(tempEncryptedOutput128, allKeys128, tempDecryptedOutput128, clk, AESDecryptEnable, aesReset128);
+    AESEncrypt #(4, 10) aese128(data, allKeys128, tempEncryptedOutput128, clk, enable, aesReset128);
+    AESDecrypt #(4, 10) aesd128(tempEncryptedOutput128, allKeys128, tempDecryptedOutput128, clk, AESDecryptEnable & enable, aesReset128);
 
     // 192-bit AES
-    wire aesReset192 = selReg == 1 ? 1'b0 : 1'b1;
+    wire aesReset192 = (reset || selReg != 1) ? 1'b1 : 1'b0;
     wire [127:0] tempEncryptedOutput192;
     wire [127:0] tempDecryptedOutput192;
     wire [1663:0] allKeys192;
 
     KeyExpansion #(6, 12) keysGetter192(key192, allKeys192);
-    AESEncrypt #(6, 12) aese192(data, allKeys192, tempEncryptedOutput192, clk, aesReset192);
-    AESDecrypt #(6, 12) aesd192(tempEncryptedOutput192, allKeys192, tempDecryptedOutput192, clk, AESDecryptEnable, aesReset192);
+    AESEncrypt #(6, 12) aese192(data, allKeys192, tempEncryptedOutput192, clk, enable, aesReset192);
+    AESDecrypt #(6, 12) aesd192(tempEncryptedOutput192, allKeys192, tempDecryptedOutput192, clk, AESDecryptEnable & enable, aesReset192);
 
     // 256-bit AES
-    wire aesReset256 = (selReg == 2 || selReg == 3) ? 1'b0 : 1'b1;
+    wire aesReset256 = (reset || selReg == 0 || selReg == 1) ? 1'b1 : 1'b0;
     wire [127:0] tempEncryptedOutput256;
     wire [127:0] tempDecryptedOutput256;
     wire [1919:0] allKeys256;
 
     KeyExpansion #(8, 14) keysGetter(key256, allKeys256);
-    AESEncrypt #(8, 14) aese256(data, allKeys256, tempEncryptedOutput256, clk, aesReset256);
-    AESDecrypt #(8, 14) aesd256(tempEncryptedOutput256, allKeys256, tempDecryptedOutput256, clk, AESDecryptEnable, aesReset256);
+    AESEncrypt #(8, 14) aese256(data, allKeys256, tempEncryptedOutput256, clk, enable, aesReset256);
+    AESDecrypt #(8, 14) aesd256(tempEncryptedOutput256, allKeys256, tempDecryptedOutput256, clk, AESDecryptEnable & enable, aesReset256);
 
     // Encrypted and Decrypted Data
     wire [127:0] tempEncryptedOutput = selReg == 0 ? tempEncryptedOutput128 : selReg == 1 ? tempEncryptedOutput192 : tempEncryptedOutput256;
@@ -65,51 +72,83 @@ module AES(LED, HEX0, HEX1, HEX2, sel, clk);
     // count = 0 -> Original Data
     // count = 1 to Nr -> Encrypted Data
     // count = Nr + 2 -> Decrypted Data
-    wire [7:0] bcdInput = (count == 0) ? data[7:0] : (count <= Nr + 1) ? tempEncryptedOutput[7:0] : tempDecryptedOutput[7:0];
+    wire [11:0] bcdInput = (count == 0) ? data[11:0] : (count <= Nr + 1) ? tempEncryptedOutput[11:0] : tempDecryptedOutput[11:0];
 
     // Binary to BCD Logic
     wire [11:0] bcdOutput;
-	Binary2BCD b2b(bcdInput, bcdOutput);
+	Binary2BCD b2b(bcdInput[7:0], bcdOutput);
 
     // 7-Segment Logic
-	DisplayDecoder dd1(bcdOutput[3:0], HEX0);
-    DisplayDecoder dd2(bcdOutput[7:4], HEX1);
-    DisplayDecoder dd3(bcdOutput[11:8], HEX2);
+    wire SevenSegEnable = ~reset;
+	DisplayDecoder dd1(bcdOutput[3:0], HEX0, SevenSegEnable);
+    DisplayDecoder dd2(bcdOutput[7:4], HEX1, SevenSegEnable);
+    DisplayDecoder dd3(bcdOutput[11:8], HEX2, SevenSegEnable);
+
+    DisplayDecoder dd4(bcdInput[3:0], HEX3, SevenSegEnable);
+    DisplayDecoder dd5(bcdInput[7:4], HEX4, SevenSegEnable);
+    DisplayDecoder dd6(bcdInput[11:8], HEX5, SevenSegEnable);
+
+    // LED = 1 if Encrypted Data has finished
+    assign LEDR[0] = count >= Nr + 1;
 
     // LED = 1 if Decrypted Data is same as original data
-    assign LED = (tempDecryptedOutput == data && count > Nr + 1);
+    assign LEDR[1] = (tempDecryptedOutput == data && count > Nr + 1);
+
+    // Mode Selection LEDs
+    assign LEDR[5] = (~reset && selReg == 0); // 128-bit AES
+    assign LEDR[6] = (~reset && selReg == 1); // 192-bit AES
+    assign LEDR[7] = (~reset && (selReg == 2 || selReg == 3)); // 256-bit AES
+
+	// Enable LED
+	assign LEDR[8] = enable;
+
+    // Reset LED
+    assign LEDR[9] = reset;
+
+    // Turn off remaining LEDs
+    assign LEDR[4:2] = 3'b0;
 
     // Previous Selection
     reg [1:0] prevSel = 2'b0;
 
-    always @(negedge clk) begin
-        prevSel = selReg;
-        selReg = sel;
-
-        if (prevSel != selReg) begin
-            prevSel = selReg;
+    always @(negedge clk or posedge reset) begin
+        if (reset) begin
+            prevSel = 2'b00;
+            selReg = sel;
             count = 0;
             AESDecryptEnable = 1'b0;
         end
-        else begin
-            if (count == Nr)
-                AESDecryptEnable = 1'b1;
-            else if (count == ((Nr + 1) * 2))
-                AESDecryptEnable = 1'b0;
+        else if (enable) begin
+            prevSel = selReg;
+            selReg = sel;
 
-            if (count <= (Nr + 1) * 2)
-                count = count + 6'b000001;
+            if (prevSel != selReg && !(selReg == 2 && prevSel == 3 || selReg == 3 && prevSel == 2)) begin
+                prevSel = selReg;
+                count = 0;
+                AESDecryptEnable = 1'b0;
+            end
+            else begin
+                if (count == Nr)
+                    AESDecryptEnable = 1'b1;
+                else if (count == ((Nr + 1) * 2))
+                    AESDecryptEnable = 1'b0;
+
+                if (count <= (Nr + 1) * 2)
+                    count = count + 6'b000001;
+            end
         end
     end
 endmodule
 
 module AES_DUT();
     reg [1:0] sel = 2'b00;
     reg clk = 1'b1;
-    wire LED;
-    wire [6:0] HEX0, HEX1, HEX2;
+    reg reset = 1'b0;
+    reg enable = 1'b1;
+    wire [9:0] LEDR;
+    wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
 
-    AES aes(LED, HEX0, HEX1, HEX2, sel, clk);
+    AES aes(LEDR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, sel, clk, reset, enable);
 
     integer count = 0;
     initial begin
@@ -121,15 +160,20 @@ module AES_DUT();
                 if (count < 80)
                     count = count + 1;
 
-                $display("Current Round Count: %0d, LED Status: %b, Encrypted State: %h (%0d), Decrypted State: %h (%0d)", count, LED, aes.tempEncryptedOutput, aes.tempEncryptedOutput[7:0], aes.tempDecryptedOutput, aes.tempDecryptedOutput[7:0]);
+                $display("\n");
+                $display("Current Round Count: %0d, Encrypted State: %h (%0d), Decrypted State: %h (%0d)", count, aes.tempEncryptedOutput, aes.tempEncryptedOutput[7:0], aes.tempDecryptedOutput, aes.tempDecryptedOutput[7:0]);
+                $display("LEDs: Reset: %0d, 256-bit AES: %0d, 192-bit AES: %0d, 128-bit AES: %0d, Decryption: %0d, Encryption: %0d", LEDR[9], LEDR[7], LEDR[6], LEDR[5], LEDR[1], LEDR[0]);
+                $display("HEX: %b (%h) %b (%h) %b (%h) %b (%0d) %b (%0d) %b (%0d)", HEX5, aes.bcdInput[11:8], HEX4, aes.bcdInput[7:4], HEX3, aes.bcdInput[3:0], HEX2, aes.bcdOutput[11:8], HEX1, aes.bcdOutput[7:4], HEX0, aes.bcdOutput[3:0]);
 
                 if (count == 23) begin
+                    $display("\n");
                     $display("==============================================");
                     $display("Switching to 192-bit AES Encryption and Decryption");
                     $display("==============================================");
                     sel = 2'b01;
                 end
                 else if (count == 50) begin
+                    $display("\n");
                     $display("==============================================");
                     $display("Switching to 256-bit AES Encryption and Decryption");
                     $display("==============================================");
@@ -141,8 +185,9 @@ module AES_DUT();
 
     initial begin
         $display("AES Encryption and Decryption");
+        $display("\n");
         $display("================================");
         $display("128-bit AES Encryption and Decryption");
         $display("================================");
     end
-endmodule
+endmodule
diff --git a/AESDecrypt.v b/AESDecrypt.v
@@ -6,7 +6,7 @@ module AESDecrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, state,
 	input reset;
 	output reg [127:0] state; // Holds the state of the AES decryption
 
-	reg [5:0] roundCount = 0; // Holds the current round count
+	reg [5:0] roundCount = 1; // Holds the current round count
 
 	wire [127:0] subByteWire;
 	wire [127:0] shiftRowsWire;
@@ -30,15 +30,9 @@ module AESDecrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, state,
 	// roundCount = 1 -> afterRoundKey
 	// roundCount = 2 to Nr -> mixColumnsWire
 	assign stateOut = (roundCount > 1 && roundCount < Nr + 1) ? mixColumnsWire : afterRoundKey;
-
-	// Assign state to data on data change and reset roundCount
-	initial @(data) begin 
-		state = data;
-		roundCount = 1;
-	end
 
 	// Update state based on roundCount
-	always @(negedge clk) begin
+	always @(negedge clk or posedge reset) begin
 		if (reset)
 			roundCount = 1;
 		else if (enable && roundCount <= Nr + 1) begin
@@ -59,7 +53,7 @@ module AESDecrypt128_DUT();
 	reg clk;
 
 	KeyExpansion #(Nk, Nr) ke(key, allKeys);
-	AESDecrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b1);
+	AESDecrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b1, 1'b0);
 
 	initial begin
 		clk = 1'b1;
@@ -78,7 +72,7 @@ module AESDecrypt192_DUT();
 	reg clk;
 
 	KeyExpansion #(Nk, Nr) ke(key, allKeys);
-	AESDecrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b1);
+	AESDecrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b1, 1'b0);
 
 	initial begin
 		clk = 1'b1;
@@ -97,7 +91,7 @@ module AESDecrypt256_DUT();
 	reg clk;
 
 	KeyExpansion ke(key, allKeys);
-	AESDecrypt aes(data, allKeys, out, clk, 1, 0);
+	AESDecrypt aes(data, allKeys, out, clk, 1'b1, 1'b0);
 
 	initial begin
 		clk = 1'b1;

diff --git a/AESEncrypt.v b/AESEncrypt.v
@@ -1,11 +1,12 @@
-module AESEncrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, state, clk, reset);
+module AESEncrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, state, clk, enable, reset);
 	input [127:0] data;
 	input [((Nr + 1) * 128) - 1:0] allKeys;
 	input clk;
 	input reset;
+	input enable;
 	output reg [127:0] state = 0; // Holds the state of the AES encryption
 
-	reg [5:0] roundCount = 0; // Holds the current round count
+	reg [5:0] roundCount = 1; // Holds the current round count
 
 	wire [127:0] subByteWire;
 	wire [127:0] shiftRowsWire;
@@ -25,19 +26,12 @@ module AESEncrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, state,
 	// roundCount = Nr + 1 -> shiftRowsWire
 	assign roundKeyInput = (roundCount == 1) ? data : (roundCount < Nr + 1) ? mixColumnsWire : shiftRowsWire;
 
-	// Assign state to data on data change and reset roundCount
-	initial @(data) begin 
-		state = data;
-		roundCount = 1;
-	end
 
 	// Update state based on roundCount
-	always @(negedge clk) begin
-		if (reset) begin
-			state = data;
+	always @(negedge clk or posedge reset) begin
+		if (reset)
 			roundCount = 1;
-		end 
-		else if (roundCount <= Nr + 1) begin
+		else if (enable && roundCount <= Nr + 1) begin
 			state = stateOut;
 			roundCount = roundCount + 6'b000001;
 		end
@@ -55,7 +49,7 @@ module AESEncrypt128_DUT();
 	reg clk;
 
 	KeyExpansion #(Nk, Nr) ke(key, allKeys);
-	AESEncrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b0);
+	AESEncrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b1, 1'b0);
 
 	initial begin
 		clk = 0;
@@ -74,7 +68,7 @@ module AESEncrypt192_DUT();
 	reg clk;
 
 	KeyExpansion #(Nk, Nr) ke(key, allKeys);
-	AESEncrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b0);
+	AESEncrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b1, 1'b0);
 
 	initial begin
 		clk = 0;
@@ -93,7 +87,7 @@ module AESEncrypt256_DUT();
 	reg clk;
 
 	KeyExpansion #(Nk, Nr) ke(key, allKeys);
-	AESEncrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b0);
+	AESEncrypt #(Nk, Nr) aes(data, allKeys, out, clk, 1'b1, 1'b0);
 
 	initial begin
 		clk = 0;

diff --git a/DisplayDecoder.v b/DisplayDecoder.v
@@ -1,20 +1,30 @@
-module DisplayDecoder(in, out);
+module DisplayDecoder(in, out, enable);
     input [3:0] in;
+    input enable;
     output reg [6:0] out;
 
-    always @(in) begin
-        case (in)
-            0 : out = 7'b1000000;
-            1 : out = 7'b1111001;
-            2 : out = 7'b0100100;
-            3 : out = 7'b0110000;
-            4 : out = 7'b0011001;
-            5 : out = 7'b0010010;
-            6 : out = 7'b0000010;
-            7 : out = 7'b1111000;
-            8 : out = 7'b0000000;
-            9 : out = 7'b0010000;
-            default : out = 7'b1111111; 
-        endcase
+    always @(in or enable) begin
+        if (!enable)
+            out = 7'b1111111;
+        else
+            case (in)
+                0 : out = 7'b1000000;
+                1 : out = 7'b1111001;
+                2 : out = 7'b0100100;
+                3 : out = 7'b0110000;
+                4 : out = 7'b0011001;
+                5 : out = 7'b0010010;
+                6 : out = 7'b0000010;
+                7 : out = 7'b1111000;
+                8 : out = 7'b0000000;
+                9 : out = 7'b0010000;
+                10 :  out = 7'b0001000;
+                11 :  out = 7'b0000011;
+                12 :  out = 7'b1000110;
+                13 :  out = 7'b0100001;
+                14 :  out = 7'b0000110;
+                15 :  out = 7'b0001110;
+                default : out = 7'b1111111; 
+            endcase
     end
 endmodule