⚡ Finalizing main module (#13)

* 🔨 Fixed display decoder

* ✨ Finalizing code for FPGA

AES.v

@@ -1,11 +1,16 @@
-module AES #(parameter Nk = 4, parameter Nr = 10) (encryptedOutputReg, decryptedOutputReg, HEX0, HEX1, HEX2, clk);
+module AES(LED, HEX0, HEX1, HEX2, clk, reset);
+	localparam Nk = 4;
+	localparam Nr = 10;
+
     input clk;
+	input reset;
+    output LED;
     output [6:0] HEX0;
     output [6:0] HEX1;
     output [6:0] HEX2;
-
-    output reg [127:0] encryptedOutputReg = 128'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00;
-    output reg [127:0] decryptedOutputReg = 128'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00;
+    output [6:0] HEX3;
+    output [6:0] HEX4;
+    output [6:0] HEX5;
 
     // Key
     wire [127:0] key = 128'h00_01_02_03_04_05_06_07_08_09_0a_0b_0c_0d_0e_0f;
@@ -20,9 +25,19 @@ module AES #(parameter Nk = 4, parameter Nr = 10) (encryptedOutputReg, decrypted
     // AES
     wire [127:0] tempEncryptedOutput;
     wire [127:0] tempDecryptedOutput;
-
+
+    // Current round count for encryption and decryption
+    reg [5:0] count;
+	initial
+		count = 0;
+
+    // Assign bcdInput based on count
+    // count = 0 -> Encrypted Data
+    // count = 1 to Nr -> Encrypted Data
+    // count = Nr + 2 -> Decrypted Data
+    wire [7:0] bcdInput = (count == 0) ? data[7:0] : (count <= Nr + 1) ? tempEncryptedOutput[7:0] : tempDecryptedOutput[7:0];
+
     // Binary to BCD Logic
-    reg [7:0] bcdInput = 8'b00000000;
     wire [11:0] bcdOutput;
 	Binary2BCD b2b(bcdInput, bcdOutput);
 
@@ -32,59 +47,54 @@ module AES #(parameter Nk = 4, parameter Nr = 10) (encryptedOutputReg, decrypted
     DisplayDecoder dd3(bcdOutput[11:8], HEX2);
 
     // Encrypt
-    reg AESEncryptEnable = 1'b1;
-    AESEncrypt AESE(data, allKeys, tempEncryptedOutput, clk, AESEncryptEnable);
+    // reg AESEncryptEnable = 1'b1;
+    AESEncrypt AESE(data, allKeys, tempEncryptedOutput, clk,reset);
 
     // Decrypt
     reg AESDecryptEnable = 1'b0;
-    AESDecrypt AESD(tempEncryptedOutput, allKeys, tempDecryptedOutput, clk, AESDecryptEnable);
+    AESDecrypt AESD(tempEncryptedOutput, allKeys, tempDecryptedOutput, clk, AESDecryptEnable,reset);
 
-    reg [4:0] count = 0;
-    always @(posedge clk) begin
-        if (AESEncryptEnable == 1 || AESDecryptEnable == 1)
-            count <= count + 1;
-    end
+    // LED = 1 if Decrypted Data is same as original data
+    assign LED = (tempDecryptedOutput == data && count > Nr + 1);
 
-    always @(count) begin
-        if (count < Nr + 1)
-            bcdInput = tempEncryptedOutput[7:0];
-        else if (count == Nr + 1) begin
-            encryptedOutputReg = tempEncryptedOutput;
-            bcdInput = tempEncryptedOutput[7:0];
-            AESEncryptEnable = 1'b0;
-            AESDecryptEnable = 1'b1;
-        end
-        else if (count < ((Nr + 1) * 2))
-            bcdInput = tempDecryptedOutput[7:0];
-        else if (count == ((Nr + 1) * 2)) begin
-            decryptedOutputReg = tempDecryptedOutput;
-            bcdInput = tempDecryptedOutput[7:0];
-            AESDecryptEnable = 1'b0;
-        end
+    always @(negedge clk) begin
+		if (reset) begin
+			count = 0;
+			AESDecryptEnable = 1'b0;
+		end
+		else begin
+			if (count == Nr)
+				AESDecryptEnable = 1'b1;
+			else if (count == ((Nr + 1) * 2))
+				AESDecryptEnable = 1'b0;
+
+            if (count <= (Nr + 1) * 2)
+                count <= count + 6'b000001;
+		end
     end
 endmodule
 
 module AES_DUT();
-    reg clk = 1'b0;
-    wire [127:0] encrypted;
-    wire [127:0] decrypted;
+    reg clk = 1'b1;
+    wire LED;
     wire [6:0] HEX0, HEX1, HEX2;
 
-    AES AES(encrypted, decrypted, HEX0, HEX1, HEX2, clk);
+    AES aes(LED, HEX0, HEX1, HEX2, clk, 1'b0);
 
-    reg [4:0] count = 5'b00000;
+    reg [5:0] count = 0;
     initial begin
-        clk = 0;
+        clk = 1'b1;
         forever begin
             #10 clk = ~clk;
-            if (clk)
+            if (!clk) begin
                 count = count + 1;
+                $display("Current Round Count: %d, LED Status: %b, Encrypted State: %h (%0d), Decrypted State: %h (%0d)", count, LED, aes.tempEncryptedOutput, aes.tempEncryptedOutput[7:0], aes.tempDecryptedOutput, aes.tempDecryptedOutput[7:0]);
+            end
         end
     end
 
     initial begin
         $display("AES Encryption and Decryption");
         $display("================================");
-        $monitor("Encrypted: %h, Decrypted: %h, Count: %d", encrypted, decrypted, count);
     end
-endmodule
+endmodule

AESDecrypt.v

@@ -1,44 +1,49 @@
-module AESDecrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, out, clk, enable);
+module AESDecrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, state, clk, enable, reset);
 	input [127:0] data;
 	input [(11 * 128) - 1:0] allKeys;
 	input clk;
 	input enable;
-	output [127:0] out;
+	input reset;
+	output reg [127:0] state; // Holds the state of the AES decryption
+
+	reg [5:0] roundCount = 0; // Holds the current round count
+
+	wire [127:0] subByteWire;
+	wire [127:0] shiftRowsWire;
+	wire [127:0] mixColumnsWire;
+	wire [127:0] afterRoundKey;
+	wire [127:0] keyInput;
+	wire [127:0] stateOut;
+
+	// Instantiate AES modules needed for decryption
+	InvShiftRows shft(state, shiftRowsWire);	
+	InvSubBytes sub(shiftRowsWire, subByteWire);
+	AddRoundKey addkey(keyInput, allKeys[((12 - roundCount) * 128 - 1) -: 128], afterRoundKey);
+	InvMixColumns mix(afterRoundKey, mixColumnsWire);
+
+	// Assign keyInput based on roundCount
+	// roundCount = 1 -> Data
+	// roundCount = 2 to Nr -> subByteWire
+	assign keyInput = (roundCount == 1) ? data : subByteWire;
+
+	// Assign stateOut based on roundCount
+	// roundCount = 1 -> afterRoundKey
+	// roundCount = 2 to Nr -> mixColumnsWire
+	assign stateOut = (roundCount > 1 && roundCount < Nr + 1) ? mixColumnsWire : afterRoundKey;
 
-	reg [127:0] state;
-	reg [127:0] keyReg; 
-	reg [3:0] roundCount = 0;
-	wire [127:0] stateAfterLastRound;
-	wire [127:0] stateAfterKey;
-	wire [127:0] stateAfterRound;
-
-	AddRoundKey a(state, keyReg , stateAfterKey);
-	DecryptRound round(state , keyReg , stateAfterRound);
-	LastDecryptRound lastRound (state , keyReg , stateAfterLastRound);
-
-	assign out = state;
-
-	always @(clk) begin
-		if (enable == 1) begin
-			if (clk) begin
-				if (roundCount == 1)
-					state <= stateAfterKey;
-				else if (roundCount < Nr +1)
-					state <= stateAfterRound;
-				else if (roundCount == Nr +1)
-					state <= stateAfterLastRound;
-
-				if (roundCount > 0 && roundCount < Nr + 1)
-					keyReg <= allKeys[((11 * 128) - roundCount * 128 - 1) -: 128];	
-
-				if (roundCount < Nr + 2)
-					roundCount <= roundCount + 1;
-			end
-			else if (roundCount == 0) begin
-				state <= data;
-				keyReg <= allKeys[((11 * 128) - 1) -: 128];
-				roundCount <= 1;
-			end
+	// Assign state to data on data change and reset roundCount
+	initial @(data) begin 
+		state = data;
+		roundCount = 1;
+	end
+
+	// Update state based on roundCount
+	always @(negedge clk) begin
+		if (reset)
+			roundCount = 1;
+		else if (enable && roundCount <= Nr + 1) begin
+			state = stateOut;				
+			roundCount = roundCount + 6'b000001;
 		end
 	end
 endmodule
@@ -51,7 +56,7 @@ module AESDecrypt_DUT();
 	reg clk;
 
 	KeyExpansion ke(key, allKeys);
-	AESDecrypt aes(data, allKeys, out, clk, 1);
+	AESDecrypt aes(data, allKeys, out, clk, 1, 0);
 
 	initial begin
 		clk = 0;

AESEncrypt.v

@@ -1,45 +1,45 @@
-module AESEncrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, out, clk, enable);
+module AESEncrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, state, clk, reset);
 	input [127:0] data;
 	input [(11 * 128) - 1:0] allKeys;
 	input clk;
-	input enable;
-	output [127:0] out;
-
-	reg [127:0] state;
-	reg [127:0] keyReg;
-	reg [3:0] roundCount = 0;
-	wire [127:0] stateAfterLastRound;
-	wire [127:0] stateAfterKey;
-	wire [127:0] stateAfterRound;
-	wire [127:0] keyWire;
-
-	AddRoundKey a(state, keyReg, stateAfterKey);
-	EncryptRound round(state, keyReg, stateAfterRound);
-	LastEncryptRound lastRound(state, keyReg, stateAfterLastRound);
-
-	assign out = state;
-
-	always @(clk) begin
-		if (enable) begin
-			if (clk) begin
-				if (roundCount == 1)
-					state <= stateAfterKey;
-				else if (roundCount < Nr + 1)
-					state <= stateAfterRound;
-				else if (roundCount == Nr + 1)
-					state <= stateAfterLastRound;
-
-				if (roundCount > 0 && roundCount < Nr + 1)
-					keyReg <= allKeys[(128 * (roundCount + 1)) - 1 -: 128];
-
-				if (roundCount < Nr + 2)
-					roundCount <= roundCount + 1;
-			end
-			else if (roundCount == 0) begin
-				state <= data;
-				keyReg <= allKeys[127 -: 128];
-				roundCount <= 1;
-			end
+	input reset;
+	output reg [127:0] state = 0; // Holds the state of the AES encryption
+
+	reg [5:0] roundCount = 0; // Holds the current round count
+
+	wire [127:0] subByteWire;
+	wire [127:0] shiftRowsWire;
+	wire [127:0] mixColumnsWire;
+	wire [127:0] roundKeyInput;
+	wire [127:0] stateOut;
+
+	// Instantiate AES modules needed for encryption
+	SubBytes sub(state, subByteWire);
+	ShiftRows shft(subByteWire, shiftRowsWire);	
+	MixColumns mix(shiftRowsWire, mixColumnsWire);	
+	AddRoundKey addkey(roundKeyInput , allKeys[(128 * roundCount) - 1 -: 128], stateOut);
+
+	// Assign roundKeyInput based on roundCount
+	// roundCount = 1 -> Data
+	// roundCount = 2 to Nr -> mixColumnsWire
+	// roundCount = Nr + 1 -> shiftRowsWire
+	assign roundKeyInput = (roundCount == 1) ? data : (roundCount < Nr + 1) ? mixColumnsWire: shiftRowsWire;
+
+	// Assign state to data on data change and reset roundCount
+	initial @(data) begin 
+		state = data;
+		roundCount = 1;
+	end
+
+	// Update state based on roundCount
+	always @(negedge clk) begin
+		if (reset) begin
+			state = data;
+			roundCount = 1;
+		end 
+		else if (roundCount <= Nr + 1) begin
+			state = stateOut;				
+			roundCount = roundCount + 6'b000001;
 		end
 	end
 endmodule
@@ -52,7 +52,7 @@ module AESEncrypt_DUT();
 	reg clk;
 
 	KeyExpansion ke(key, allKeys);
-	AESEncrypt aes(data, allKeys, out, clk, 1);
+	AESEncrypt aes(data, allKeys, out, clk, 0);
 
 	initial begin
 		clk = 0;

Binary2BCD.v

@@ -3,7 +3,7 @@ module CondAdd3(in, out);
     input [3:0] in;
     output [3:0] out;
 
-    assign out = in >= 5 ? in + 3:in;
+    assign out = in >= 5 ? in + 4'b0011 : in;
 endmodule
 
 module Binary2BCD(in, out);

DisplayDecoder.v

@@ -1,23 +1,20 @@
 module DisplayDecoder(in, out);
-	input [3:0] in;
-    output [6:0] out;
+    input [3:0] in;
+    output reg [6:0] out;
 
-    reg [6:0] display7;
-
-    assign out = display7;
-
-	always @(in)
-		case(in)
-            0 : display7 = 7'b0000001;
-            1 : display7 = 7'b1001111;
-            2 : display7 = 7'b0010010;
-            3 : display7 = 7'b0000110;
-            4 : display7 = 7'b1001100;
-            5 : display7 = 7'b0100100;
-            6 : display7 = 7'b0100000;
-            7 : display7 = 7'b0001111;
-            8 : display7 = 7'b0000000;
-            9 : display7 = 7'b0000100;
-            default : display7 = 7'b1111111; 
+    always @(in) begin
+        case (in)
+            0 : out = 7'b1000000;
+            1 : out = 7'b1111001;
+            2 : out = 7'b0100100;
+            3 : out = 7'b0110000;
+            4 : out = 7'b0011001;
+            5 : out = 7'b0010010;
+            6 : out = 7'b0000010;
+            7 : out = 7'b1111000;
+            8 : out = 7'b0000000;
+            9 : out = 7'b0010000;
+            default : out = 7'b1111111; 
         endcase
+    end
 endmodule