Merge pull request #3 from AhmedSobhy01/shift-bin2bcd

🙌 ShiftRows & InvShiftRows & Bin2BCD

Binary2BCD.v

@@ -0,0 +1,26 @@
+
+module  CondAdd3(input[3:0]in,output[3:0]out);
+
+    assign out = in >= 5 ? in + 3 : in;
+
+endmodule
+
+
+
+module Binary2BCD(in , out);
+    input [7:0] in;
+    output [11:0] out;
+    wire [28 : 1] temp;
+
+    CondAdd3 c1( {0,in[7:5]}, temp[4 : 1]  );
+    CondAdd3 c2( {temp[3:1] , in[4]}, temp[8 : 5]  );
+    CondAdd3 c3( {temp[7:5] , in[3]}, temp[12 : 9]  );
+    CondAdd3 c4( {temp[11:9] , in[2]}, temp[16 : 13]  );
+    CondAdd3 c5( {temp[15:13] , in[1]}, temp[20 : 17]  );
+    CondAdd3 c6( {0 , temp[4] , temp[8] , temp[12] }, temp[24 : 21]  );
+    CondAdd3 c7( {temp[23:21] , temp[16] }, temp[28 : 25]  );
+
+    assign out = { 0 , 0 , temp[24] , temp[28:25] , temp[20:17] , in[0]};
+
+
+endmodule

Binary2BCD_tb.v

@@ -0,0 +1,48 @@
+module Binary2BCD_tb();
+
+    reg [7:0] in;
+    wire [11:0] out;
+
+    Binary2BCD Binary2BCD_dut(
+    .in(in),
+    .out(out)
+);
+
+
+
+    initial begin
+    in = 1;
+    # 50;
+    in = 112;  
+    # 50;
+    in = 251;
+    # 50;
+    in = 0;
+    # 50;
+    in = 156;
+    # 50;
+    in = 045;
+    # 50;
+    in = 255;
+    # 50;
+    in = 100;
+    # 50;
+    in = 124;
+    # 50;
+    in = 235;
+    # 50;
+    in = 050;
+
+
+
+    end
+
+    always @ (in) begin
+    $display("\nin = %d", in);
+
+    $display("\nout = %b", out);
+
+
+    end
+
+endmodule

InvShiftRows .v

@@ -0,0 +1,53 @@
+module InvShiftRows( in , out );
+input [127 : 0 ] in;
+output [127 : 0 ] out ;
+// S(0,0) in[127:120]
+// S(0,1) in[95:88]
+// S(0,2) in[63:56]
+// S(0,3) in[31:24]
+//--------------------
+// S(1,0) in[119:112]
+// S(1,1) in[87:80]
+// S(1,2) in[55:48]
+// S(1,3) in[23:16]
+//--------------------
+// S(2,0) in[111:104]
+// S(2,1) in[79:72]
+// S(2,2) in[47:40]
+// S(2,3) in[15:8]
+//--------------------
+// S(3,0) in[103:96]
+// S(3,1) in[71:64]
+// S(3,2) in[39:32]
+// S(3,3) in[7:0]
+//--------------------
+
+
+
+//1st row no shift
+assign out[127:120] = in[127:120];
+assign out[95:88] = in[95:88];
+assign out[63:56] = in[63:56];
+assign out[31:24] = in[31:24];
+//2nd row shift 1
+assign out[119:112] = in[23:16];
+assign out[87:80] = in[119:112];
+assign out[55:48] = in[87:80];
+assign out[23:16] = in[55:48];
+//3rd row shift 2
+assign out[111:104] = in[47:40];
+assign out[79:72] = in[15:8];
+assign out[47:40] = in[111:104];
+assign out[15:8] = in[79:72];
+//4th row shift 3
+assign out[103:96] = in[71:64];
+assign out[71:64] = in[39:32];
+assign out[39:32] = in[7:0];
+assign out[7:0] = in[103:96];
+
+
+
+
+
+
+endmodule

InvShiftRows_tb.v

@@ -0,0 +1,24 @@
+module InvShiftRows_tb();
+ reg [127 : 0 ] in;
+ wire  [127 : 0 ] out ;
+
+initial begin
+in = 128'h_aa5ece06ee6e3c56dde68bac2621bebf;
+# 50;
+in = 128'h_d1ed44fd1a0f3f2afa4ff27b7c332a69;  
+end
+
+
+
+InvShiftRows InvShiftRows_dut(
+    .in(in),
+    .out(out)
+);
+
+always @ (in) begin
+    $display("in = %h", in);
+    $display("out = %h", out);
+
+end
+
+endmodule

ShiftRows.v

@@ -0,0 +1,53 @@
+module ShiftRows( in , out );
+input [127 : 0 ] in;
+output [127 : 0 ] out ;
+// S(0,0) in[127:120]
+// S(0,1) in[95:88]
+// S(0,2) in[63:56]
+// S(0,3) in[31:24]
+//--------------------
+// S(1,0) in[119:112]
+// S(1,1) in[87:80]
+// S(1,2) in[55:48]
+// S(1,3) in[23:16]
+//--------------------
+// S(2,0) in[111:104]
+// S(2,1) in[79:72]
+// S(2,2) in[47:40]
+// S(2,3) in[15:8]
+//--------------------
+// S(3,0) in[103:96]
+// S(3,1) in[71:64]
+// S(3,2) in[39:32]
+// S(3,3) in[7:0]
+//--------------------
+
+
+
+//1st row no shift
+assign out[127:120] = in[127:120];
+assign out[95:88] = in[95:88];
+assign out[63:56] = in[63:56];
+assign out[31:24] = in[31:24];
+//2nd row shift 1
+assign out[119:112] = in[87:80];
+assign out[87:80] = in[55:48];
+assign out[55:48] = in[23:16];
+assign out[23:16] = in[119:112];
+//3rd row shift 2
+assign out[111:104] = in[47:40];
+assign out[79:72] = in[15:8];
+assign out[47:40] = in[111:104];
+assign out[15:8] = in[79:72];
+//4th row shift 3
+assign out[103:96] = in[7:0];
+assign out[71:64] = in[103:96];
+assign out[39:32] = in[71:64];
+assign out[7:0] = in[39:32];
+
+
+
+
+
+
+endmodule

ShiftRows_tb.v

@@ -0,0 +1,24 @@
+module ShiftRows_tb();
+ reg [127 : 0 ] in;
+ wire  [127 : 0 ] out ;
+
+initial begin
+in = 128'h_adcb0f257e9c63e0bc557e951c15ef01;
+# 50;
+in = 128'h_884a33781fdb75c2d380349e19f876fb;  
+end
+
+
+
+ShiftRows ShiftRows_dut(
+    .in(in),
+    .out(out)
+);
+
+always @ (in) begin
+    $display("in = %h", in);
+    $display("out = %h", out);
+
+end
+
+endmodule