diff --git a/drivers/disk/Kconfig.sdmmc b/drivers/disk/Kconfig.sdmmc index 42d82676b18f28..8d8f560db76549 100644 --- a/drivers/disk/Kconfig.sdmmc +++ b/drivers/disk/Kconfig.sdmmc @@ -37,7 +37,7 @@ config SDMMC_STM32 select USE_STM32_HAL_MMC if SDMMC_STM32_EMMC select USE_STM32_HAL_MMC_EX if SDMMC_STM32_EMMC && SOC_SERIES_STM32L4X select USE_STM32_LL_SDMMC - select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X) + select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F1X) select DMA if $(DT_STM32_SDMMC_HAS_DMA) && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X) select PINCTRL select RESET diff --git a/drivers/disk/sdmmc_stm32.c b/drivers/disk/sdmmc_stm32.c index 114e7d6b467ab2..4507ecd245ee84 100644 --- a/drivers/disk/sdmmc_stm32.c +++ b/drivers/disk/sdmmc_stm32.c @@ -21,6 +21,7 @@ LOG_MODULE_REGISTER(stm32_sdmmc, CONFIG_SDMMC_LOG_LEVEL); #define STM32_SDMMC_USE_DMA DT_NODE_HAS_PROP(DT_DRV_INST(0), dmas) +#define STM32_SDMMC_USE_RESET !DT_NODE_HAS_COMPAT(DT_DRV_INST(0), st_stm32f1_sdmmc) #if STM32_SDMMC_USE_DMA #include @@ -84,7 +85,9 @@ struct stm32_sdmmc_priv { struct gpio_dt_spec pe; struct stm32_pclken *pclken; const struct pinctrl_dev_config *pcfg; +#if STM32_SDMMC_USE_RESET const struct reset_dt_spec reset; +#endif #if STM32_SDMMC_USE_DMA struct sdmmc_dma_stream dma_rx; @@ -302,11 +305,13 @@ static int stm32_sdmmc_access_init(struct disk_info *disk) return err; } +#if STM32_SDMMC_USE_RESET err = reset_line_toggle_dt(&priv->reset); if (err) { LOG_ERR("failed to reset peripheral"); return err; } +#endif #ifdef CONFIG_SDMMC_STM32_EMMC err = HAL_MMC_Init(&priv->hsd); @@ -690,10 +695,12 @@ static int disk_stm32_sdmmc_init(const struct device *dev) return -ENODEV; } +#if STM32_SDMMC_USE_RESET if (!device_is_ready(priv->reset.dev)) { LOG_ERR("reset control device not ready"); return -ENODEV; } +#endif /* Configure dt provided device signals when available */ err = pinctrl_apply_state(priv->pcfg, PINCTRL_STATE_DEFAULT); @@ -812,7 +819,9 @@ static struct stm32_sdmmc_priv stm32_sdmmc_priv_1 = { #endif .pclken = pclken_sdmmc, .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), +#if STM32_SDMMC_USE_RESET .reset = RESET_DT_SPEC_INST_GET(0), +#endif SDMMC_DMA_CHANNEL(rx, RX) SDMMC_DMA_CHANNEL(tx, TX) }; diff --git a/dts/arm/st/f1/stm32f103Xc.dtsi b/dts/arm/st/f1/stm32f103Xc.dtsi index d2a609a22de471..bc8bf8c2cfeb84 100644 --- a/dts/arm/st/f1/stm32f103Xc.dtsi +++ b/dts/arm/st/f1/stm32f103Xc.dtsi @@ -159,7 +159,7 @@ #dma-cells = <2>; reg = <0x40020400 0x400>; clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; - interrupts = < 56 0 57 0 58 0 59 0 60 0>; + interrupts = < 56 0 57 0 58 0 59 0>; status = "disabled"; }; }; diff --git a/dts/arm/st/f1/stm32f103Xe.dtsi b/dts/arm/st/f1/stm32f103Xe.dtsi index 18c0dcc83ff2b2..e622a4f811e94f 100644 --- a/dts/arm/st/f1/stm32f103Xe.dtsi +++ b/dts/arm/st/f1/stm32f103Xe.dtsi @@ -18,5 +18,39 @@ erase-block-size = ; }; }; + + i2s2: i2s@40003800 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + interrupts = <36 5>; + dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s3: i2s@40003c00 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + interrupts = <51 5>; + dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + sdmmc1: sdmmc@40018000 { + compatible = "st,stm32f1-sdmmc", "st,stm32-sdmmc"; + reg = <0x40018000 0x400>; + clocks = <&rcc STM32_CLOCK(AHB1, 10U)>; + interrupts = <49 0>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/st/f1/stm32f103Xg.dtsi b/dts/arm/st/f1/stm32f103Xg.dtsi index a40a4c40361696..6bcc93c6adb83b 100644 --- a/dts/arm/st/f1/stm32f103Xg.dtsi +++ b/dts/arm/st/f1/stm32f103Xg.dtsi @@ -29,6 +29,32 @@ }; }; + i2s2: i2s@40003800 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + interrupts = <36 5>; + dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s3: i2s@40003c00 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + interrupts = <51 5>; + dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + timers9: timers@40014c00 { compatible = "st,stm32-timers"; reg = <0x40014c00 0x400>; diff --git a/dts/arm/st/f1/stm32f105Xc.dtsi b/dts/arm/st/f1/stm32f105Xc.dtsi index e2151b445485ce..b1fc75532307cf 100644 --- a/dts/arm/st/f1/stm32f105Xc.dtsi +++ b/dts/arm/st/f1/stm32f105Xc.dtsi @@ -18,5 +18,31 @@ reg = <0x08000000 DT_SIZE_K(256)>; }; }; + + i2s2: i2s@40003800 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + interrupts = <36 5>; + dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s3: i2s@40003c00 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + interrupts = <51 5>; + dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; }; diff --git a/dts/arm/st/f1/stm32f107Xc.dtsi b/dts/arm/st/f1/stm32f107Xc.dtsi index ea7ad2e491ccd7..e5f0b4e233eb5d 100644 --- a/dts/arm/st/f1/stm32f107Xc.dtsi +++ b/dts/arm/st/f1/stm32f107Xc.dtsi @@ -18,5 +18,31 @@ reg = <0x08000000 DT_SIZE_K(256)>; }; }; + + i2s2: i2s@40003800 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 14U)>; + interrupts = <36 5>; + dmas = <&dma1 5 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma1 4 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s3: i2s@40003c00 { + compatible = "st,stm32-i2s"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003c00 0x400>; + clocks = <&rcc STM32_CLOCK(APB1, 15U)>; + interrupts = <51 5>; + dmas = <&dma2 2 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) + &dma2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; }; diff --git a/dts/bindings/mmc/st,stm32f1-sdmmc.yaml b/dts/bindings/mmc/st,stm32f1-sdmmc.yaml new file mode 100644 index 00000000000000..3db3cf52dd7949 --- /dev/null +++ b/dts/bindings/mmc/st,stm32f1-sdmmc.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Benjamin Björnsson benjamin.bjornsson@gmail.com + +# SPDX-License-Identifier: Apache-2.0 + +description: | + ST STM32F1 family SDIO + Remove the resets property since there's no reset register + for AHB peripherals on F1 series. + +compatible: "st,stm32f1-sdmmc" + +include: + - name: st,stm32-sdmmc.yaml + property-blocklist: + - resets diff --git a/west.yml b/west.yml index 1d27186b2e9f4c..3d02dba4a3ec2f 100644 --- a/west.yml +++ b/west.yml @@ -233,7 +233,7 @@ manifest: groups: - hal - name: hal_stm32 - revision: 019d8255333f96bdd47d26b44049bd3e7af8ef55 + revision: pull/239/head path: modules/hal/stm32 groups: - hal