diff --git a/firmware/python/cameralink_gateway/_ClinkDevRoot.py b/firmware/python/cameralink_gateway/_ClinkDevRoot.py
index 8ebdc5f..bec9d68 100644
--- a/firmware/python/cameralink_gateway/_ClinkDevRoot.py
+++ b/firmware/python/cameralink_gateway/_ClinkDevRoot.py
@@ -50,6 +50,7 @@ def __init__(self,
                  enableDump     = False,
                  enableConfig   = True,
                  pcieBoardType  = None,
+                 useDdr         = False,
                  enVcMask       = 0xD, # Enable lane mask: Don't connect data stream (VC1) by default because intended for C++ process
                  zmqSrvEn       = True,  # Flag to include the ZMQ server
                  **kwargs):
@@ -111,6 +112,7 @@ def __init__(self,
             enLclsI    = enLclsI,
             enLclsII   = enLclsII,
             boardType  = pcieBoardType,
+            useDdr     = useDdr,
             expand     = True,
         ))
 
diff --git a/firmware/python/cameralink_gateway/_ClinkPcieFpga.py b/firmware/python/cameralink_gateway/_ClinkPcieFpga.py
index dd3a957..4abbd2a 100644
--- a/firmware/python/cameralink_gateway/_ClinkPcieFpga.py
+++ b/firmware/python/cameralink_gateway/_ClinkPcieFpga.py
@@ -12,6 +12,7 @@
 
 import axipcie                 as pcie
 import lcls2_pgp_fw_lib.shared as shared
+import surf.axi                as axi
 
 class ClinkPcieFpga(pr.Device):
     def __init__(self,
@@ -20,6 +21,7 @@ def __init__(self,
                  enLclsI    = True,
                  enLclsII   = False,
                  boardType  = None,
+                 useDdr     = False,
                  **kwargs):
         super().__init__(**kwargs)
 
@@ -31,6 +33,14 @@ def __init__(self,
             expand      = False,
         ))
 
+        if useDdr:
+            for i in range(4):
+                self.add(axi.AxiStreamDmaV2Fifo(
+                    name    = f'DmaBuffer[{i}]',
+                    offset  = 0x0010_0000+i*0x100,
+                    expand  = False,
+                ))
+
         # Application layer
         self.add(shared.ApplicationLaneConfigDict(
             offset     = 0x00C0_0000,
diff --git a/software/scripts/devGui.py b/software/scripts/devGui.py
index 3d164a9..ad9726e 100755
--- a/software/scripts/devGui.py
+++ b/software/scripts/devGui.py
@@ -175,6 +175,12 @@ def __call__( self , parser, namespace,values, option_string = None):
         help     = "Sets the GUI type (PyDM or None)",
     )
 
+    parser.add_argument(
+        "--ddr",
+        action   = 'store_true',
+        help     = "Includes on-board DDR support",
+    )
+
     # Get the arguments
     args = parser.parse_args()
 
@@ -219,6 +225,7 @@ def __call__( self , parser, namespace,values, option_string = None):
             pgp4           = args.pgp4,
             seuDumpDir     = args.seuDumpDir,
             pcieBoardType  = args.pcieBoardType,
+            useDdr         = args.ddr,
             enVcMask       = args.enVcMask,
         ) as root: