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Opening this issue to hopefully provoke adding support for System Verilog. I like using this editor but it would be nice if there was System Verilog support as I require it for a project I am working on.
Possible solution could be to extend the Verilog mode such that it also provides highlighting for the additional System Verilog keywords.
The text was updated successfully, but these errors were encountered:
Opening this issue to hopefully provoke adding support for System Verilog. I like using this editor but it would be nice if there was System Verilog support as I require it for a project I am working on.
Possible solution could be to extend the Verilog mode such that it also provides highlighting for the additional System Verilog keywords.
The text was updated successfully, but these errors were encountered: