From 1b37475aa29ece7c574c89640dd6db56eb578a86 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Tue, 10 Dec 2024 16:57:06 +0000 Subject: [PATCH] Minor fix in systems appendix --- src/system.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/system.adoc b/src/system.adoc index e56d7019..cb43bf4e 100644 --- a/src/system.adoc +++ b/src/system.adoc @@ -44,7 +44,7 @@ All writes from the system port to the memory must clear any memory tags to foll image::large_cheri_system.drawio.png[width=80%,align=center] In the case of a large CHERI SoC with caches, all the cached memory visible to the CHERI CPUs must support tags. -All memory is backed up by DRAM, and standard DRAM does not offer 129-bit words and so a typical system will have a tag cache IP. +All memory is backed up by DRAM, and standard DRAM does not offer CLEN+1 bit words and so a typical system will have a tag cache IP. A region of DRAM is reserved for CHERI tag storage.