diff --git a/library/CMakeLists.txt b/library/CMakeLists.txt index 12eded40..c085a63e 100644 --- a/library/CMakeLists.txt +++ b/library/CMakeLists.txt @@ -9,9 +9,11 @@ Crystal.lib Diodes.lib DiodesSchottky.lib Diodes_Extended.lib +Digital_AUX.lib Digital_CD.lib Digital_HC.lib Digital_LV.lib +Digital_XSPICE.lib GeDiodes.lib Ideal.lib JFETs.lib diff --git a/library/Digital_AUX.lib b/library/Digital_AUX.lib new file mode 100644 index 00000000..c8c6cc27 --- /dev/null +++ b/library/Digital_AUX.lib @@ -0,0 +1,1027 @@ + + + + +Analog Clock +Based on Analog Pulse source + + +.Def:Digital_AUX_Clock _net0 _net1 Freq="10MEG" Vhigh="1" Vlow="0" Tt="0.1ns" Tdelay="0" +Sub:X1 _net0 _net1 gnd Type="Clock_cir" +.Def:End + + + +* Analog User selectable Clock Source based on the Analog Pulse source +* +.subckt clk out+ out- freq=10MEG vlow=0 vhigh=1 tdelay=0 tt=0.1ns +* +* Assume Ttransit=Trise=Tfall, Tt=Tr=Tf +* PER = 1/freq +* PW = (PER/2)-Tt +* PULSE(V1 V2 TD TR TF PW PER) +* +vclk out+ out- dc 0 pulse('vlow' 'vhigh' 'tdelay' 'tt' 'tt' '(((1/freq)/2)-tt)' '1/freq') +* +.ends clk + +.SUBCKT Digital_AUX_Clock gnd _net0 _net1 Freq=10MEG Vhigh=1 Vlow=0 Tt=0.1ns Tdelay=0 +X1 _net0 _net1 clk FREQ=FREQ VLOW=VLOW VHIGH=VHIGH TDELAY=TDELAY TT=TT +.ENDS + + + + + + + + + + + + + <.PortSym 0 40 2 0 Out_n> + <.PortSym 40 0 1 180 Out_p> + <.ID 14 25 CLK "1=Freq=10MEG=Clock Frequency (Hz)=" "1=Vhigh=1=Output High Voltage (volts)=" "1=Vlow=0=Output Low Voltage (volts)=" "1=Tt=0.1ns=Output Rise/Fall times (sec)=" "1=Tdelay=0=Output Time Delay (sec)="> + + + + + + + +Digital Clock +Based on Analog Pulse source +followed by ADC Bridge + + +.Def:Digital_AUX_d_Clock _net1 _net0 Freq="10MEG" Tdelay="0" rise_delay="1ps" fall_delay="1ps" +Sub:X1 _net1 _net0 gnd Type="d_Clock_cir" +.Def:End + + + +* XSPICE Digital User selectable Clock based on the Analog Pulse source followed by ADC Bridge +* +.subckt d_clk 0 dout freq=10MEG tdelay=0 rise_delay=1ps fall_delay=1ps +* +* Assume Ttransit=tt=TR=TF=1ps +* PER = 1/freq +* PW = (PER/2)-tt +* PULSE(V1 V2 TD TR TF PW PER) +* +vclk aout 0 dc 0 pulse(0 1 'tdelay' 1ps 1ps '(((1/freq)/2)-1ps)' '1/freq') +* +* ADC Bridge - single line +* Analog-in -> Digital-out +* +abridge1 [aout] [dout] adc1 +.model adc1 adc_bridge(in_low=0.5 in_high=0.5 rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends d_clk + +.SUBCKT Digital_AUX_d_Clock gnd _net1 _net0 Freq=10MEG Tdelay=0 rise_delay=1ps fall_delay=1ps +X1 _net1 _net0 d_clk FREQ=FREQ TDELAY=TDELAY RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + + + + + + + + + + + + + <.ID 14 25 CLK "1=Freq=10MEG=Clock Frequency (Hz)=" "1=Tdelay=0=Output Time Delay (sec)=" "1=rise_delay=1ps=Rise Delay (sec)=" "1=fall_delay=1ps=Fall Delay (sec)="> + <.PortSym 40 0 2 180 dout> + <.PortSym 0 40 1 0 rtn> + + + + + +XSPICE VCO +Based on d-osc +Digital Output +Analog Output 1 Volt + + +.Def:Digital_AUX_VCO_XSPICE _net0 _net2 _net1 c1="0.5" c2="1" c3="1.5" c4="2" c5="2.5" c6="3" c7="3.5" c8="4" c9="4.5" f1="6e6" f2="7e6" f3="8e6" f4="9e6" f5="10e6" f6="11e6" f7="12e6" f8="13e6" f9="14e6" +Sub:X1 _net0 _net2 _net1 gnd Type="VCO_dosc_cir" +.Def:End + + + +***** XSPICE digital controlled oscillator d_osc as vco *************** +* 6 MHz to 14 MHz +* name: d_osc_vco +* aout analog output +* dout digital output +* cont control voltage +* +.subckt d_osc_vco dout aout cont ++ params: c1=0.5 c2=1 c3=1.5 c4=2 c5=2.5 c6=3 c7=3.5 c8=4 c9=4.5 ++ params: f1=6e6 f2=7e6 f3=8e6 f4=9e6 f5=10e6 f6=11e6 f7=12e6 f8=13e6 f9=14e6 +* +a1 cont dout clock +.model clock d_osc(cntl_array = [c1 c2 c3 c4 c5 c6 c7 c8 c9] ++ freq_array = [f1 f2 f3 f4 f5 f6 f7 f8 f9] ++ duty_cycle = 0.5 init_phase = 180.0001 ; bug won't let "180.0" work ++ rise_delay = 1e-14 fall_delay=1e-14) + +*generate an analog output +abridge-fit [dout] [aout] dac1 +.model dac1 dac_bridge(out_low=0 out_high=1 input_load=1e-12 t_rise=1e-12 t_fall=1e-12) + +.ends d_osc_vco + +.SUBCKT Digital_AUX_VCO_XSPICE gnd _net0 _net2 _net1 c1=0.5 c2=1 c3=1.5 c4=2 c5=2.5 c6=3 c7=3.5 c8=4 c9=4.5 f1=6e6 f2=7e6 f3=8e6 f4=9e6 f5=10e6 f6=11e6 f7=12e6 f8=13e6 f9=14e6 +X1 _net0 _net2 _net1 d_osc_vco c1=c1 c2=c2 c3=c3 c4=c4 c5=c5 c6=c6 c7=c7 c8=c8 c9=c9 f1=f1 f2=f2 f3=f3 f4=f4 f5=f5 f6=f6 f7=f7 f8=f8 f9=f9 +.ENDS + + + + + + + + + + + + + + + + + + + + + + <.PortSym -40 0 3 0 cont> + <.PortSym 40 -10 1 180 dout> + <.PortSym 40 10 2 180 aout> + <.ID 30 14 VCO "1=c1=0.5=Control Voltage Array (Volts)=" "1=c2=1=Control Voltage Array (Volts)=" "1=c3=1.5=Control Voltage Array (Volts)=" "1=c4=2=Control Voltage Array (Volts)=" "1=c5=2.5=Control Voltage Array (Volts)=" "1=c6=3=Control Voltage Array (Volts)=" "1=c7=3.5=Control Voltage Array (Volts)=" "1=c8=4=Control Voltage Array (Volts)=" "1=c9=4.5=Control Voltage Array (Volts)=" "1=f1=6e6=Frequency Array (Hertz)=" "1=f2=7e6=Frequency Array (Hertz)=" "1=f3=8e6=Frequency Array (Hertz)=" "1=f4=9e6=Frequency Array (Hertz)=" "1=f5=10e6=Frequency Array (Hertz)=" "1=f6=11e6=Frequency Array (Hertz)=" "1=f7=12e6=Frequency Array (Hertz)=" "1=f8=13e6=Frequency Array (Hertz)=" "1=f9=14e6=Frequency Array (Hertz)="> + + + + + +XSPICE ADC Bridge x1 + + +.Def:Digital_AUX_ADC_bridge _net0 _net1 in_low="0.5" in_high="0.5" rise_delay="1e-9" fall_delay="1e-9" +Sub:X1 _net0 _net1 gnd Type="ADC_bridge_cir" +.Def:End + + + +* ADC Bridge - single line +* Analog-in -> Digital-out +.subckt adcbridge Ain Dout in_low=0.5 in_high=0.5 rise_delay=1e-9 fall_delay=1e-9 +* +abridge [Ain] [Dout] adc1 ; ngspice only accepts names starting with "a" +* +.model adc1 adc_bridge(in_low='in_low' in_high='in_high' rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends adcbridge + +.SUBCKT Digital_AUX_ADC_bridge gnd _net0 _net1 in_low=0.5 in_high=0.5 rise_delay=1e-9 fall_delay=1e-9 +X1 _net0 _net1 adcbridge IN_LOW=IN_LOW IN_HIGH=IN_HIGH RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + + + + + + + + <.PortSym -60 0 1 0 Ain> + <.PortSym 60 0 2 180 Dout> + <.ID -20 14 XS "1=in_low=0.5=Maximum 0-valued analog input (Volts)=" "1=in_high=0.5=Minimum 1-valued analog input (Volts)=" "1=rise_delay=1e-9=Rise Delay (sec)=" "1=fall_delay=1e-9=Fall Delay (sec)="> + D"> + + + + + +XSPICE ADC Bridge x4 + + +.Def:Digital_AUX_ADC_bridge_4 _net0 _net1 _net2 _net5 _net3 _net6 _net4 _net7 in_low="0.5" in_high="0.5" rise_delay="1e-9" fall_delay="1e-9" +Sub:X1 _net0 _net1 _net2 _net5 _net3 _net6 _net4 _net7 gnd Type="ADC_bridge_4_cir" +.Def:End + + + +* ADC Bridge - four line +* Analog-in -> Digital-out +.subckt adcbridge4 Ain1 Dout1 Ain2 Dout2 Ain3 Dout3 Ain4 Dout4 in_low=0.5 in_high=0.5 rise_delay=1e-9 fall_delay=1e-9 +* +abridge [Ain1 Ain2 Ain3 Ain4] [Dout1 Dout2 Dout3 Dout4] adc1 ; ngspice only accepts names starting with "a" +* +.model adc1 adc_bridge(in_low='in_low' in_high='in_high' rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends adcbridge4 + +.SUBCKT Digital_AUX_ADC_bridge_4 gnd _net0 _net1 _net2 _net5 _net3 _net6 _net4 _net7 in_low=0.5 in_high=0.5 rise_delay=1e-9 fall_delay=1e-9 +X1 _net0 _net1 _net2 _net5 _net3 _net6 _net4 _net7 adcbridge4 IN_LOW=IN_LOW IN_HIGH=IN_HIGH RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + <.PortSym -50 -30 1 0 Ain1> + <.PortSym 70 -30 2 180 Dout1> + + + + + + + + + + + + + + + + + + + + + + + + + + + + D"> + D"> + D"> + D"> + <.PortSym -50 -10 3 0 Ain2> + <.PortSym -50 10 5 0 Ain3> + <.PortSym -50 30 7 0 Ain4> + <.PortSym 70 -10 4 180 Dout2> + <.PortSym 70 10 6 180 Dout3> + <.PortSym 70 30 8 180 Dout4> + <.ID -20 44 XS "1=in_low=0.5=Maximum 0-valued analog input (Volts)=" "1=in_high=0.5=Minimum 1-valued analog input (Volts)=" "1=rise_delay=1e-9=Rise Delay (sec)=" "1=fall_delay=1e-9=Fall Delay (sec)="> + + + + + +XSPICE ADC Bridge x8 + + +.Def:Digital_AUX_ADC_bridge_8 _net0 _net1 _net2 _net5 _net3 _net6 _net4 _net7 _net8 _net9 _net10 _net11 _net12 _net13 _net14 _net15 in_low="0.5" in_high="0.5" rise_delay="1e-9" fall_delay="1e-9" +Sub:X1 _net0 _net1 _net2 _net5 _net3 _net6 _net4 _net7 _net8 _net9 _net10 _net11 _net12 _net13 _net14 _net15 gnd Type="ADC_bridge_8_cir" +.Def:End + + + +* ADC Bridge - eight line +* Analog-in -> Digital-out +.subckt adcbridge8 Ain1 Dout1 Ain2 Dout2 Ain3 Dout3 Ain4 Dout4 Ain5 Dout5 Ain6 Dout6 Ain7 Dout7 Ain8 Dout8 in_low=0.5 in_high=0.5 rise_delay=1e-9 fall_delay=1e-9 +* +abridge [Ain1 Ain2 Ain3 Ain4 Ain5 Ain6 Ain7 Ain8] [Dout1 Dout2 Dout3 Dout4 Dout5 Dout6 Dout7 Dout8] adc1 ; ngspice only accepts names starting with "a" +* +.model adc1 adc_bridge(in_low='in_low' in_high='in_high' rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends adcbridge8 + +.SUBCKT Digital_AUX_ADC_bridge_8 gnd _net0 _net1 _net2 _net5 _net3 _net6 _net4 _net7 _net8 _net9 _net10 _net11 _net12 _net13 _net14 _net15 in_low=0.5 in_high=0.5 rise_delay=1e-9 fall_delay=1e-9 +X1 _net0 _net1 _net2 _net5 _net3 _net6 _net4 _net7 _net8 _net9 _net10 _net11 _net12 _net13 _net14 _net15 adcbridge8 IN_LOW=IN_LOW IN_HIGH=IN_HIGH RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + <.PortSym -60 -70 1 0 Ain1> + <.PortSym 60 -70 2 180 Dout1> + <.PortSym -60 -50 3 0 Ain2> + <.PortSym -60 -30 5 0 Ain3> + <.PortSym -60 -10 7 0 Ain4> + <.PortSym 60 -50 4 180 Dout2> + <.PortSym 60 -30 6 180 Dout3> + <.PortSym 60 -10 8 180 Dout4> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D"> + D"> + D"> + D"> + D"> + D"> + D"> + D"> + <.PortSym -60 10 9 0 Ain5> + <.PortSym -60 30 11 0 Ain6> + <.PortSym -60 50 13 0 Ain7> + <.PortSym -60 70 15 0 Ain8> + <.PortSym 60 10 10 180 Dout5> + <.PortSym 60 30 12 180 Dout6> + <.PortSym 60 50 14 180 Dout7> + <.PortSym 60 70 16 180 Dout8> + <.ID -30 84 XS "1=in_low=0.5=Maximum 0-valued analog input (Volts)=" "1=in_high=0.5=Minimum 1-valued analog input (Volts)=" "1=rise_delay=1e-9=Rise Delay (sec)=" "1=fall_delay=1e-9=Fall Delay (sec)="> + + + + + +XSPICE DAC Bridge x1 + + +.Def:Digital_AUX_DAC_bridge _net0 _net1 out_low="0" out_high="1" out_undef="0.5" input_load="1e-12" t_rise="1e-9" t_fall="1e-9" +Sub:X1 _net0 _net1 gnd Type="DAC_bridge_cir" +.Def:End + + + +* DAC Bridge - single line +* Digital-in -> Analog-out +.subckt dacbridge Din Aout out_low=0 out_high=1 out_undef=0.5 input_load=1e-12 t_rise=1e-9 t_fall=1e-9 +* +abridge [Din] [Aout] dac1 ; ngspice only accepts names starting with "a" +* +.model dac1 dac_bridge(out_low='out_low' out_high='out_high' out_undef='out_undef' input_load='input_load' t_rise='t_rise' t_fall='t_fall') +* +.ends dacbridge + +.SUBCKT Digital_AUX_DAC_bridge gnd _net0 _net1 out_low=0 out_high=1 out_undef=0.5 input_load=1e-12 t_rise=1e-9 t_fall=1e-9 +X1 _net0 _net1 dacbridge OUT_LOW=OUT_LOW OUT_UNDEF=OUT_UNDEF OUT_HIGH=OUT_HIGH INPUT_LOAD=INPUT_LOAD T_RISE=T_RISE T_FALL=T_FALL +.ENDS + + + <.PortSym -60 0 1 0 Din> + <.PortSym 60 0 2 180 Aout> + + + + + + + + A"> + <.ID -20 14 XS "1=out_low=0=0-valued analog output (Volts)=" "1=out_high=1=1-valued analog output (Volts)=" "1=out_undef=0.5=U-valued analog output (Volts)=" "1=input_load=1e-12=Input load (F)=" "1=t_rise=1e-9=Rise time 0->1 (sec)=" "1=t_fall=1e-9=Fall time 1->0 (sec)="> + + + + + +XSPICE DAC Bridge x4 + + +.Def:Digital_AUX_DAC_bridge_4 _net0 _net1 _net2 _net3 _net5 _net4 _net6 _net7 out_low="0" out_high="1" out_undef="0.5" input_load="1e-12" t_rise="1e-9" t_fall="1e-9" +Sub:X1 _net0 _net1 _net2 _net3 _net5 _net4 _net6 _net7 gnd Type="DAC_bridge_4_cir" +.Def:End + + + +* DAC Bridge - four line +* Digital-in -> Analog-out +.subckt dacbridge4 Din1 Aout1 Din2 Aout2 Din3 Aout3 Din4 Aout4 out_low=0 out_high=1 out_undef=0.5 input_load=1e-12 t_rise=1e-9 t_fall=1e-9 +* +abridge [Din1 Din2 Din3 Din4] [Aout1 Aout2 Aout3 Aout4] dac1 ; ngspice only accepts names starting with "a" +* +.model dac1 dac_bridge(out_low='out_low' out_high='out_high' out_undef='out_undef' input_load='input_load' t_rise='t_rise' t_fall='t_fall') +* +.ends dacbridge4 + +.SUBCKT Digital_AUX_DAC_bridge_4 gnd _net0 _net1 _net2 _net3 _net5 _net4 _net6 _net7 out_low=0 out_high=1 out_undef=0.5 input_load=1e-12 t_rise=1e-9 t_fall=1e-9 +X1 _net0 _net1 _net2 _net3 _net5 _net4 _net6 _net7 dacbridge4 OUT_LOW=OUT_LOW OUT_UNDEF=OUT_UNDEF OUT_HIGH=OUT_HIGH INPUT_LOAD=INPUT_LOAD T_RISE=T_RISE T_FALL=T_FALL +.ENDS + + + <.PortSym -50 -30 1 0 Din1> + <.PortSym -50 -10 3 0 Din2> + <.PortSym -50 10 5 0 Din3> + <.PortSym 70 -30 2 180 Aout1> + <.PortSym 70 -10 4 180 Aout2> + <.PortSym 70 10 6 180 Aout3> + <.PortSym 70 30 8 180 Aout4> + <.PortSym -50 30 7 0 Din4> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + A"> + A"> + A"> + A"> + <.ID -20 44 XS "1=out_low=0=0-valued analog output (Volts)=" "1=out_high=1=1-valued analog output (Volts)=" "1=out_undef=0.5=U-valued analog output (Volts)=" "1=input_load=1e-12=Input load (F)=" "1=t_rise=1e-9=Rise time 0->1 (sec)=" "1=t_fall=1e-9=Fall time 1->0 (sec)="> + + + + + +XSPICE DAC Bridge x8 + + +.Def:Digital_AUX_DAC_bridge_8 _net0 _net1 _net2 _net3 _net5 _net4 _net6 _net7 _net8 _net9 _net10 _net11 _net13 _net12 _net15 _net14 out_low="0" out_high="1" out_undef="0.5" input_load="1e-12" t_rise="1e-9" t_fall="1e-9" +Sub:X1 _net0 _net1 _net2 _net3 _net5 _net4 _net6 _net7 _net8 _net9 _net10 _net11 _net13 _net12 _net15 _net14 gnd Type="DAC_bridge_8_cir" +.Def:End + + + +* DAC Bridge - eight line +* Digital-in -> Analog-out +.subckt dacbridge8 Din1 Aout1 Din2 Aout2 Din3 Aout3 Din4 Aout4 Din5 Aout5 Din6 Aout6 Din7 Aout7 Din8 Aout8 out_low=0 out_high=1 out_undef=0.5 input_load=1e-12 t_rise=1e-9 t_fall=1e-9 +* +abridge [Din1 Din2 Din3 Din4 Din5 Din6 Din7 Din8] [Aout1 Aout2 Aout3 Aout4 Aout5 Aout6 Aout7 Aout8] dac1 ; ngspice only accepts names starting with "a" +* +.model dac1 dac_bridge(out_low='out_low' out_high='out_high' out_undef='out_undef' input_load='input_load' t_rise='t_rise' t_fall='t_fall') +* +.ends dacbridge8 + +.SUBCKT Digital_AUX_DAC_bridge_8 gnd _net0 _net1 _net2 _net3 _net5 _net4 _net6 _net7 _net8 _net9 _net10 _net11 _net13 _net12 _net15 _net14 out_low=0 out_high=1 out_undef=0.5 input_load=1e-12 t_rise=1e-9 t_fall=1e-9 +X1 _net0 _net1 _net2 _net3 _net5 _net4 _net6 _net7 _net8 _net9 _net10 _net11 _net13 _net12 _net15 _net14 dacbridge8 OUT_LOW=OUT_LOW OUT_UNDEF=OUT_UNDEF OUT_HIGH=OUT_HIGH INPUT_LOAD=INPUT_LOAD T_RISE=T_RISE T_FALL=T_FALL +.ENDS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + A"> + A"> + A"> + A"> + A"> + A"> + A"> + A"> + <.PortSym -60 -70 1 0 Din1> + <.PortSym -60 -50 3 0 Din2> + <.PortSym -60 -30 5 0 Din3> + <.PortSym -60 -10 7 0 Din4> + <.PortSym 60 -70 2 180 Aout1> + <.PortSym 60 -50 4 180 Aout2> + <.PortSym 60 -30 6 180 Aout3> + <.PortSym 60 -10 8 180 Aout4> + <.PortSym -60 10 9 0 Din5> + <.PortSym -60 30 11 0 Din6> + <.PortSym -60 50 13 0 Din7> + <.PortSym -60 70 15 0 Din8> + <.PortSym 60 10 10 180 Aout5> + <.PortSym 60 30 12 180 Aout6> + <.PortSym 60 50 14 180 Aout7> + <.PortSym 60 70 16 180 Aout8> + <.ID -30 84 XS "1=out_low=0=0-valued analog output (Volts)=" "1=out_high=1=1-valued analog output (Volts)=" "1=out_undef=0.5=U-valued analog output (Volts)=" "1=input_load=1e-12=Input load (F)=" "1=t_rise=1e-9=Rise time 0->1 (sec)=" "1=t_fall=1e-9=Fall time 1->0 (sec)="> + + + + + +XSPICE Digital to Real Bridge + + +.Def:Digital_AUX_D2R_bridge _net1 _net2 _net0 Zero="0" One="1" delay="1e-9" +Sub:X1 _net1 _net2 _net0 gnd Type="D2R_bridge_cir" +.Def:End + + + +* D2R Bridge - single line +* Digital-in -> Real-out Unique to ngspice +.subckt d2rbridge Din En Rout zero=0 one=1 delay=1e-9 +* +abridge Din En Rout dr1 ; ngspice only accepts names starting with "a" +* +.model dr1 d_to_real (zero='zero' one='one' delay='delay') +* +.ends d2rbridge + +.SUBCKT Digital_AUX_D2R_bridge gnd _net1 _net2 _net0 Zero=0 One=1 delay=1e-9 +X1 _net1 _net2 _net0 d2rbridge ZERO=ZERO ONE=ONE DELAY=DELAY +.ENDS + + + <.PortSym -60 0 1 0 Din> + + + + + + + R"> + <.ID -20 14 XS "1=Zero=0=value for 0, < one value=" "1=One=1=value for 1, >zero value=" "1=delay=1e-9=delay (sec)="> + + + <.PortSym -10 -30 2 0 En> + <.PortSym 60 0 3 180 Rout> + + + + + + +XSPICE Real to Voltage Bridge + + +.Def:Digital_AUX_R2V_bridge _net0 _net1 Gain="1" transition_time="1e-9" +Sub:X1 _net0 _net1 gnd Type="R2V_bridge_cir" +.Def:End + + + +* R2V Bridge - single line +* Real-in -> Digital-out Unique to ngspice +.subckt r2vbridge Rin Vout gain=1 transition_time=1e-9 +* +abridge Rin Vout dr1 ; ngspice only accepts names starting with "a" +* +.model dr1 real_to_v (gain='gain' transition_time='transition_time') +* +.ends r2vbridge + +.SUBCKT Digital_AUX_R2V_bridge gnd _net0 _net1 Gain=1 transition_time=1e-9 +X1 _net0 _net1 r2vbridge GAIN=GAIN TRANSITION_TIME=TRANSITION_TIME +.ENDS + + + <.PortSym -60 0 1 0 Rin> + + + + + + + + V"> + <.PortSym 60 0 2 180 Vout> + <.ID -20 14 XS "1=Gain=1=Gain=" "1=transition_time=1e-9=transition time (sec)="> + + + + + +XSPICE Digital Logic 0 +Analog Voltage Source '0V' +followed by ADC Bridge + + +.Def:Digital_AUX_Logic_zero _net0 +Sub:X1 _net0 gnd Type="PS_Logic_0_lib" +.Def:End + + + +* PSpice Digital Logic 0 +* +.SUBCKT Logic_0 _net0 +VS int 0 DC 0 +abridge2 [int] [_net0] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) +.ENDS Logic_0 + +.SUBCKT Digital_AUX_Logic_zero gnd _net0 +X1 _net0 Logic_0 +.ENDS + + + + + + + + + + <.PortSym 30 0 1 180 Net0> + <.ID -10 -35 Y> + + + + + +XSPICE Digital Logic 1 +Analog Voltage Source '1V' +followed by ADC Bridge + + +.Def:Digital_AUX_Logic_one _net0 +Sub:X1 _net0 gnd Type="PS_Logic_1_lib" +.Def:End + + + +* PSpice Digital Logic 1 +* +.SUBCKT Logic_1 _net0 +VS int 0 DC 1 +abridge2 [int] [_net0] adc_buff +.model adc_buff adc_bridge(in_low = 0.5 in_high = 0.5) +.ENDS Logic_1 + +.SUBCKT Digital_AUX_Logic_one gnd _net0 +X1 _net0 Logic_1 +.ENDS + + + + + + + + + + <.PortSym 30 0 1 180 Net0> + <.ID -10 -35 Y> + + + + + +XSPICE Digital Pull-Down +Based on d_pulldown + + +.Def:Digital_AUX_d_pulldown _net0 +Sub:X1 _net0 gnd Type="d_pulldown_cir" +.Def:End + + + +* Digital "zero" +* +.subckt pulldown d_zero +* +a1 d_zero pulldown1 +.model pulldown1 d_pulldown(load=20.0e-12) +* +.ends pulldown + +.SUBCKT Digital_AUX_d_pulldown gnd _net0 +X1 _net0 pulldown +.ENDS + + + + + + + + + + <.PortSym 30 0 1 180 d_zero> + <.ID -10 -36 Y> + + + + + +XSPICE Digital Pull-Up +Based on d_pullup + + +.Def:Digital_AUX_d_pullup _net0 +Sub:X1 _net0 gnd Type="d_pullup_cir" +.Def:End + + + +* Digital "one" +* +.subckt pullup d_one +* +a1 d_one pullup1 +.model pullup1 d_pullup(load=20.0e-12) +* +.ends pullup + +.SUBCKT Digital_AUX_d_pullup gnd _net0 +X1 _net0 pullup +.ENDS + + + + + + + + + + <.PortSym 30 0 1 180 d_one> + <.ID -10 -36 Y> + + + + + +Resistor Termination x4 + + +.Def:Digital_AUX_R_Term4 _net0 _net4 _net1 _net2 _net3 RT="1k" +R:R1 _net0 _net4 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R2 _net0 _net1 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R3 _net0 _net2 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R4 _net0 _net3 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +Eqn:Eqn1 RT="RT" Export="Export=yes" +.Def:End + + +.SUBCKT Digital_AUX_R_Term4 gnd _net0 _net4 _net1 _net2 _net3 RT=1k +.PARAM RT=RT +R1 _net0 _net4 {RT} tc1=0.0 tc2=0.0 +R2 _net0 _net1 {RT} tc1=0.0 tc2=0.0 +R3 _net0 _net2 {RT} tc1=0.0 tc2=0.0 +R4 _net0 _net3 {RT} tc1=0.0 tc2=0.0 +.ENDS + + + + + + + + + + + + + + + + + + <.ID 50 -6 RT "1=RT=1k=Resistance Value (Ohms)="> + <.PortSym -30 -20 2 0 T1> + <.PortSym -10 -20 3 0 T2> + <.PortSym 10 -20 4 0 T3> + <.PortSym 30 -20 5 0 T4> + + <.PortSym 0 20 1 0 COM> + + + + + +Resistor Termination x8 + + +.Def:Digital_AUX_R_Term8 _net0 _net4 _net1 _net2 _net3 _net5 _net6 _net7 _net8 RT="1k" +R:R1 _net0 _net4 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R2 _net0 _net1 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R3 _net0 _net2 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R4 _net0 _net3 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R5 _net0 _net5 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R6 _net0 _net6 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R7 _net0 _net7 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R8 _net0 _net8 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +Eqn:Eqn1 RT="RT" Export="Export=yes" +.Def:End + + +.SUBCKT Digital_AUX_R_Term8 gnd _net0 _net4 _net1 _net2 _net3 _net5 _net6 _net7 _net8 RT=1k +.PARAM RT=RT +R1 _net0 _net4 {RT} tc1=0.0 tc2=0.0 +R2 _net0 _net1 {RT} tc1=0.0 tc2=0.0 +R3 _net0 _net2 {RT} tc1=0.0 tc2=0.0 +R4 _net0 _net3 {RT} tc1=0.0 tc2=0.0 +R5 _net0 _net5 {RT} tc1=0.0 tc2=0.0 +R6 _net0 _net6 {RT} tc1=0.0 tc2=0.0 +R7 _net0 _net7 {RT} tc1=0.0 tc2=0.0 +R8 _net0 _net8 {RT} tc1=0.0 tc2=0.0 +.ENDS + + + + + + + + + + + + + + + + + + <.PortSym 0 20 1 0 COM> + + + + + + <.PortSym -70 -20 2 0 T1> + <.PortSym -50 -20 3 0 T2> + <.PortSym -30 -20 4 0 T3> + <.PortSym -10 -20 5 0 T4> + <.PortSym 10 -20 6 0 T5> + <.PortSym 30 -20 7 0 T6> + <.PortSym 50 -20 8 0 T7> + <.PortSym 70 -20 9 0 T8> + <.ID 90 -6 RT "1=RT=1k=Resistance Value (Ohms)="> + + + + + +Resistor Termination x10 + + +.Def:Digital_AUX_R_Term10 _net0 _net4 _net1 _net2 _net3 _net5 _net6 _net7 _net8 _net9 _net10 RT="1k" +R:R1 _net0 _net4 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R2 _net0 _net1 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R3 _net0 _net2 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R4 _net0 _net3 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R5 _net0 _net5 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R6 _net0 _net6 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R7 _net0 _net7 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R8 _net0 _net8 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +Eqn:Eqn1 RT="RT" Export="Export=yes" +R:R9 _net0 _net9 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +R:R10 _net0 _net10 R="RT" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85" +.Def:End + + +.SUBCKT Digital_AUX_R_Term10 gnd _net0 _net4 _net1 _net2 _net3 _net5 _net6 _net7 _net8 _net9 _net10 RT=1k +.PARAM RT=RT +R1 _net0 _net4 {RT} tc1=0.0 tc2=0.0 +R2 _net0 _net1 {RT} tc1=0.0 tc2=0.0 +R3 _net0 _net2 {RT} tc1=0.0 tc2=0.0 +R4 _net0 _net3 {RT} tc1=0.0 tc2=0.0 +R5 _net0 _net5 {RT} tc1=0.0 tc2=0.0 +R6 _net0 _net6 {RT} tc1=0.0 tc2=0.0 +R7 _net0 _net7 {RT} tc1=0.0 tc2=0.0 +R8 _net0 _net8 {RT} tc1=0.0 tc2=0.0 +R9 _net0 _net9 {RT} tc1=0.0 tc2=0.0 +R10 _net0 _net10 {RT} tc1=0.0 tc2=0.0 +.ENDS + + + + + + + + + + + + + + + + + + <.PortSym 0 20 1 0 COM> + + + + + <.ID 110 -6 RT "1=RT=1k=Resistance Value (Ohms)="> + + + + <.PortSym -90 -20 2 0 T1> + <.PortSym -70 -20 3 0 T2> + <.PortSym -50 -20 4 0 T3> + <.PortSym -30 -20 5 0 T4> + <.PortSym -10 -20 6 0 T5> + <.PortSym 10 -20 7 0 T6> + <.PortSym 30 -20 8 0 T7> + <.PortSym 50 -20 9 0 T8> + <.PortSym 70 -20 10 0 T9> + <.PortSym 90 -20 11 0 T10> + + diff --git a/library/Digital_XSPICE.lib b/library/Digital_XSPICE.lib new file mode 100644 index 00000000..9a88cae8 --- /dev/null +++ b/library/Digital_XSPICE.lib @@ -0,0 +1,988 @@ + + + + +2-Input AND +XSPICE Based + + +.Def:Digital_XSPICE_d_AND2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net2 _net1 gnd Type="d_and2_cir" +.Def:End + + + +**** XSPICE digital 2-Input AND **** +* +.subckt d_and2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B] Y and1 +.model and1 d_and(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_and2X + +.SUBCKT Digital_XSPICE_d_AND2 gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net2 _net1 d_and2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + + + + + + <.PortSym -30 10 2 0 B> + <.PortSym 30 0 3 180 Y> + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + <.PortSym -30 -10 1 0 A> + + + + + +3-Input AND +XSPICE Based + + +.Def:Digital_XSPICE_d_AND3 _net0 _net1 _net2 _net3 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 _net3 gnd Type="d_and3_cir" +.Def:End + + + +**** XSPICE digital 3-Input AND **** +* +.subckt d_and3X A B C Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B C] Y and1 +.model and1 d_and(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_and3X + +.SUBCKT Digital_XSPICE_d_AND3 gnd _net0 _net1 _net2 _net3 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 _net3 d_and3X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + + + + + + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + <.PortSym -30 -10 1 0 A> + + <.PortSym -30 0 2 0 B> + <.PortSym -30 10 3 0 C> + <.PortSym 30 0 4 180 Y> + + + + + +4-Input AND +XSPICE Based + + +.Def:Digital_XSPICE_d_AND4 _net0 _net1 _net2 _net3 _net4 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 _net3 _net4 gnd Type="d_and4_cir" +.Def:End + + + +**** XSPICE digital 4-Input AND **** +* +.subckt d_and4X A B C D Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B C D] Y and1 +.model and1 d_and(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_and4X + +.SUBCKT Digital_XSPICE_d_AND4 gnd _net0 _net1 _net2 _net3 _net4 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 _net3 _net4 d_and4X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 -30 1 0 A> + <.PortSym -30 -10 2 0 B> + <.PortSym -30 10 3 0 C> + <.PortSym -30 30 4 0 D> + <.PortSym 40 0 5 180 Y> + <.ID 20 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + + + + + + + + + + +8-Input AND +XSPICE Based + + +.Def:Digital_XSPICE_d_AND8 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 gnd Type="d_and8_cir" +.Def:End + + + +**** XSPICE digital 8-Input AND **** +* +.subckt d_and8X A B C D E F G H Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B C D E F G H] Y and1 +.model and1 d_and(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_and8X + +.SUBCKT Digital_XSPICE_d_AND8 gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 d_and8X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.ID 20 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + + + + + + + + + <.PortSym -30 -70 1 0 A> + <.PortSym -30 -50 2 0 B> + <.PortSym -30 -30 3 0 C> + <.PortSym -30 -10 4 0 D> + <.PortSym -30 10 5 0 E> + <.PortSym -30 30 6 0 F> + <.PortSym -30 50 7 0 G> + <.PortSym -30 70 8 0 H> + <.PortSym 40 0 9 180 Y> + + + + + + +2-Input NAND +XSPICE Based + + +.Def:Digital_XSPICE_d_NAND2 _net0 _net1 _net2 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 gnd Type="d_nand2_cir" +.Def:End + + + +**** XSPICE digital 2-Input NAND **** +* +.subckt d_nand2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B] Y nand1 +.model nand1 d_nand(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_nand2X + +.SUBCKT Digital_XSPICE_d_NAND2 gnd _net0 _net1 _net2 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 d_nand2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 10 2 0 B> + <.PortSym 30 0 3 180 Y> + <.PortSym -30 -10 1 0 A> + + + + + + + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + +3-Input NAND +XSPICE Based + + +.Def:Digital_XSPICE_d_NAND3 _net0 _net1 _net2 _net3 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 _net3 gnd Type="d_nand3_cir" +.Def:End + + + +**** XSPICE digital 3-Input NAND **** +* +.subckt d_nand3X A B C Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B C] Y nand1 +.model nand1 d_nand(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_nand3X + + +.SUBCKT Digital_XSPICE_d_NAND3 gnd _net0 _net1 _net2 _net3 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 _net3 d_nand3X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 -10 1 0 A> + + + + + + + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + <.PortSym -30 0 2 0 B> + <.PortSym -30 10 3 0 C> + <.PortSym 30 0 4 180 Y> + + + + + +4-Input NAND +XSPICE Based + + +.Def:Digital_XSPICE_d_NAND4 _net0 _net1 _net2 _net3 _net4 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 _net3 _net4 gnd Type="d_nand4_cir" +.Def:End + + + +**** XSPICE digital 4-Input NAND **** +* +.subckt d_nand4X A B C D Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B C D] Y nand1 +.model nand1 d_nand(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_nand4X + + +.SUBCKT Digital_XSPICE_d_NAND4 gnd _net0 _net1 _net2 _net3 _net4 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 _net3 _net4 d_nand4X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + + + + + + <.PortSym -30 -30 1 0 A> + <.PortSym -30 -10 2 0 B> + <.PortSym -30 10 3 0 C> + <.PortSym -30 30 4 0 D> + <.PortSym 40 0 5 180 Y> + + + + + + <.ID 20 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + +8-Input NAND +XSPICE Based + + +.Def:Digital_XSPICE_d_NAND8 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 gnd Type="d_nand8_cir" +.Def:End + + + +**** XSPICE digital 8-Input AND **** +* +.subckt d_nand8X A B C D E F G H Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B C D E F G H] Y nand1 +.model nand1 d_nand(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_nand8X + +.SUBCKT Digital_XSPICE_d_NAND8 gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 d_nand8X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.ID 20 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + + + + + + + + <.PortSym -30 -70 1 0 A> + <.PortSym -30 -50 2 0 B> + <.PortSym -30 -30 3 0 C> + <.PortSym -30 -10 4 0 D> + <.PortSym -30 10 5 0 E> + <.PortSym -30 30 6 0 F> + <.PortSym -30 50 7 0 G> + <.PortSym -30 70 8 0 H> + <.PortSym 40 0 9 180 Y> + + + + + + + + +2-Input OR +XSPICE Based + + +.Def:Digital_XSPICE_d_OR2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net2 _net1 gnd Type="d_or2_cir" +.Def:End + + + +**** XSPICE digital 2-Input OR **** +* +.subckt d_or2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B] Y or1 +.model or1 d_or(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_or2X + +.SUBCKT Digital_XSPICE_d_OR2 gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net2 _net1 d_or2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 10 2 0 B> + <.PortSym 30 0 3 180 Y> + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + <.PortSym -30 -10 1 0 A> + + + + + + + + + + + + +3-Input OR +XSPICE Based + + +.Def:Digital_XSPICE_d_OR3 _net0 _net1 _net2 _net3 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 _net3 gnd Type="d_or3_cir" +.Def:End + + + +**** XSPICE digital 3-Input OR **** +* +.subckt d_or3X A B C Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B C] Y or1 +.model or1 d_or(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_or3X + +.SUBCKT Digital_XSPICE_d_OR3 gnd _net0 _net1 _net2 _net3 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 _net3 d_or3X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 -10 1 0 A> + + + + + + + + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + <.PortSym -30 0 2 0 B> + <.PortSym -30 10 3 0 C> + <.PortSym 30 0 4 180 Y> + + + + + +2-Input NOR +XSPICE Based + + +.Def:Digital_XSPICE_d_NOR2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net2 _net1 gnd Type="d_nor2_cir" +.Def:End + + + +**** XSPICE digital 2-Input NOR **** +* +.subckt d_nor2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B] Y nor1 +.model nor1 d_nor(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_nor2X + +.SUBCKT Digital_XSPICE_d_NOR2 gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net2 _net1 d_nor2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 10 2 0 B> + <.PortSym 30 0 3 180 Y> + <.PortSym -30 -10 1 0 A> + + + + + + + + + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + +2-Input NOR +XSPICE Based + + +.Def:Digital_XSPICE_d_NOR3 _net0 _net1 _net2 _net3 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 _net2 _net3 gnd Type="d_nor3_cir" +.Def:End + + + +**** XSPICE digital 3-Input NOR **** +* +.subckt d_nor3X A B C Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B C] Y nor1 +.model nor1 d_nor(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_nor3X + +.SUBCKT Digital_XSPICE_d_NOR3 gnd _net0 _net1 _net2 _net3 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 _net2 _net3 d_nor3X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 -10 1 0 A> + + + + + + + + + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + <.PortSym -30 0 2 0 B> + <.PortSym -30 10 3 0 C> + <.PortSym 30 0 4 180 Y> + + + + + +2-Input XOR +XSPICE Based + + +.Def:Digital_XSPICE_d_XOR2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net2 _net1 gnd Type="d_xor2_cir" +.Def:End + + + +**** XSPICE digital 2-Input XOR **** +* +.subckt d_xor2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B] Y xor1 +.model xor1 d_xor(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_xor2X + +.SUBCKT Digital_XSPICE_d_XOR2 gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net2 _net1 d_xor2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 10 2 0 B> + <.PortSym 30 0 3 180 Y> + <.PortSym -30 -10 1 0 A> + + + + + + + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + +2-Input XNOR +XSPICE Based + + +.Def:Digital_XSPICE_d_XNOR2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net2 _net1 gnd Type="d_nor2_cir" +.Def:End + + + +**** XSPICE digital 2-Input NOR **** +* +.subckt d_nor2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 [A B] Y nor1 +.model nor1 d_nor(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_nor2X + +.SUBCKT Digital_XSPICE_d_XNOR2 gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net2 _net1 d_nor2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.PortSym -30 10 2 0 B> + <.PortSym 30 0 3 180 Y> + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + <.PortSym -30 -10 1 0 A> + + + + + + + + + + + + +Digital Buffer +XSPICE Based + + +.Def:Digital_XSPICE_d_BUF _net0 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 gnd Type="d_buf_cir" +.Def:End + + + +**** XSPICE digital Buffer **** +* +.subckt d_bufX A Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 A Y buf1 +.model buf1 d_buffer(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_bufX + +.SUBCKT Digital_XSPICE_d_BUF gnd _net0 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 d_bufX RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + + + + + + <.PortSym -30 0 1 0 A> + <.PortSym 30 0 2 180 Y> + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + +Digital Inverter +XSPICE Based + + +.Def:Digital_XSPICE_d_INV _net0 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12" +Sub:X1 _net0 _net1 gnd Type="d_inv_cir" +.Def:End + + + +**** XSPICE digital Inverter **** +* +.subckt d_invX A Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12 +* +a1 A Y inv1 +.model inv1 d_inverter(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load') +* +.ends d_invX + +.SUBCKT Digital_XSPICE_d_INV gnd _net0 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 +X1 _net0 _net1 d_invX RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD +.ENDS + + + <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)="> + + + + + <.PortSym -30 0 1 0 A> + <.PortSym 30 0 2 180 Y> + + + + + + + +Tri-State Buffer +XSPICE Based + + +.Def:Digital_XSPICE_d_TRI _net0 _net2 _net1 Delay="1e-10" Input_Load="0.5e-12" Enable_Load="0.5e-12" +SpLib:X1 _net0 _net2 _net1 File="d_tri.cir" Device="D_TRIX" SymPattern="auto" Params="DELAY=DELAY INPUT_LOAD=INPUT_LOAD ENABLE_LOAD=ENABLE_LOAD" PinAssign="" +.Def:End + + +.SUBCKT Digital_XSPICE_d_TRI gnd _net0 _net2 _net1 Delay=1e-10 Input_Load=0.5e-12 Enable_Load=0.5e-12 +XX1 _net0 _net2 _net1 D_TRIX DELAY=DELAY INPUT_LOAD=INPUT_LOAD ENABLE_LOAD=ENABLE_LOAD +.ENDS + + +module Sub_Digital_XSPICE_d_TRI (net_net0, net_net2, net_net1); + inout net_net0, net_net1, net_net2; + + parameter Delay = 1e-10; + parameter Input_Load = 0.5e-12; + parameter Enable_Load = 0.5e-12; + +endmodule + + +library ieee; +use ieee.std_logic_1164.all; +entity Sub_Digital_XSPICE_d_TRI is + generic (Delay : real := 1e-10; + Input_Load : real := 0.5e-12; + Enable_Load : real := 0.5e-12; + ); + port (net_net0 : inout ; + net_net2 : inout ; + net_net1 : inout ); +end entity; +use work.all; +architecture Arch_Sub_Digital_XSPICE_d_TRI of Sub_Digital_XSPICE_d_TRI is +begin +end architecture; + + + + + + + + <.PortSym -30 0 1 0 A> + <.PortSym 30 0 3 180 Y> + <.ID 20 14 Y "1=Delay=1e-10=Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=" "1=Enable_Load=0.5e-12=Enable Load (F)="> + + <.PortSym 0 20 2 0 E> + + + + + +D Flip-Flop +XSPICE Based + + +.Def:Digital_XSPICE_d_D_FF _net0 _net1 _net4 _net5 _net2 _net3 Clk_Delay="1e-10" Set_Delay="1e-10" Reset_Delay="1e-10" IC="0" Rise_Delay="1e-10" Fall_Delay="1e-10" +Sub:X1 _net0 _net1 _net4 _net5 _net2 _net3 gnd Type="d_dff_cir" +.Def:End + + + +* XSPICE d_dff Digital D Flip-Flop +* +.subckt d_ff d_d d_c d_set d_reset d_q d_q_ clk_delay=1.0e-10 set_delay=1.0e-10 reset_delay=1.0e-10 ic=0 rise_delay=1.0e-10 fall_delay=1e-10 +* +ad1 d_d d_c d_set d_reset d_q d_q_ flop1 +.model flop1 d_dff(clk_delay='clk_delay' set_delay='set_delay' reset_delay='reset_delay' ic='ic' rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends d_dff + +.SUBCKT Digital_XSPICE_d_D_FF gnd _net0 _net1 _net4 _net5 _net2 _net3 Clk_Delay=1e-10 Set_Delay=1e-10 Reset_Delay=1e-10 IC=0 Rise_Delay=1e-10 Fall_Delay=1e-10 +X1 _net0 _net1 _net4 _net5 _net2 _net3 d_ff CLK_DELAY=CLK_DELAY SET_DELAY=SET_DELAY RESET_DELAY=RESET_DELAY IC=IC RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + + + + + + + + + + + + <.PortSym -50 -20 1 0 D> + <.PortSym -50 20 2 0 C> + <.PortSym 50 -20 5 180 Q> + <.PortSym 50 20 6 180 Q_> + + + + + <.PortSym 0 60 4 0 Reset> + <.PortSym 0 -60 3 0 Set> + <.ID 20 44 Y "1=Clk_Delay=1e-10=Clock Delay (sec)=" "1=Set_Delay=1e-10=Set Delay (sec)=" "1=Reset_Delay=1e-10=Reset Delay (sec)=" "1=IC=0=Output Initial State=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)="> + + + + + +D Flip-Flop +Set-Reset Swapped +XSPICE Based + + +.Def:Digital_XSPICE_d_D_FF_B _net0 _net1 _net4 _net5 _net2 _net3 Clk_Delay="1e-10" Set_Delay="1e-10" Reset_Delay="1e-10" IC="0" Rise_Delay="1e-10" Fall_Delay="1e-10" +Sub:X1 _net0 _net1 _net4 _net5 _net2 _net3 gnd Type="d_dff_cir" +.Def:End + + + +* XSPICE d_dff Digital D Flip-Flop +* +.subckt d_ff d_d d_c d_set d_reset d_q d_q_ clk_delay=1.0e-10 set_delay=1.0e-10 reset_delay=1.0e-10 ic=0 rise_delay=1.0e-10 fall_delay=1e-10 +* +ad1 d_d d_c d_set d_reset d_q d_q_ flop1 +.model flop1 d_dff(clk_delay='clk_delay' set_delay='set_delay' reset_delay='reset_delay' ic='ic' rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends d_dff + +.SUBCKT Digital_XSPICE_d_D_FF_B gnd _net0 _net1 _net4 _net5 _net2 _net3 Clk_Delay=1e-10 Set_Delay=1e-10 Reset_Delay=1e-10 IC=0 Rise_Delay=1e-10 Fall_Delay=1e-10 +X1 _net0 _net1 _net4 _net5 _net2 _net3 d_ff CLK_DELAY=CLK_DELAY SET_DELAY=SET_DELAY RESET_DELAY=RESET_DELAY IC=IC RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + + + + + + + + + + + + <.PortSym -50 -20 1 0 D> + <.PortSym -50 20 2 0 C> + <.PortSym 50 -20 5 180 Q> + <.PortSym 50 20 6 180 Q_> + + + <.ID 20 44 Y "1=Clk_Delay=1e-10=Clock Delay (sec)=" "1=Set_Delay=1e-10=Set Delay (sec)=" "1=Reset_Delay=1e-10=Reset Delay (sec)=" "1=IC=0=Output Initial State=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)="> + + + <.PortSym 0 -60 4 0 Reset> + <.PortSym 0 60 3 0 Set> + + + + + +JK Flip-Flop +XSPICE Based + + +.Def:Digital_XSPICE_d_JK_FF _net0 _net3 _net1 _net5 _net6 _net4 _net2 Clk_Delay="1e-10" Set_Delay="1e-10" Reset_Delay="1e-10" IC="0" Rise_Delay="1e-10" Fall_Delay="1e-10" +Sub:X1 _net0 _net3 _net1 _net5 _net6 _net4 _net2 gnd Type="d_jkff_cir" +.Def:End + + + +* XSPICE d_jkff Digital J-K Flip-Flop +* +.subckt d_jkff d_j d_k d_c d_set d_reset d_q d_q_ clk_delay=1.0e-10 set_delay=1.0e-10 reset_delay=1.0e-10 ic=0 rise_delay=1.0e-10 fall_delay=1e-10 +* +ad1 d_j d_k d_c d_set d_reset d_q d_q_ flop1 +.model flop1 d_jkff(clk_delay='clk_delay' set_delay='set_delay' reset_delay='reset_delay' ic='ic' rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends d_jkff + +.SUBCKT Digital_XSPICE_d_JK_FF gnd _net0 _net3 _net1 _net5 _net6 _net4 _net2 Clk_Delay=1e-10 Set_Delay=1e-10 Reset_Delay=1e-10 IC=0 Rise_Delay=1e-10 Fall_Delay=1e-10 +X1 _net0 _net3 _net1 _net5 _net6 _net4 _net2 d_jkff CLK_DELAY=CLK_DELAY SET_DELAY=SET_DELAY RESET_DELAY=RESET_DELAY IC=IC RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + + + + + + + + + + <.PortSym -50 -20 1 0 J> + <.PortSym -50 20 2 0 K> + + + + + + + + <.PortSym -50 0 3 0 C> + <.PortSym 0 -60 4 0 Set> + <.PortSym 0 60 5 0 Reset> + <.PortSym 50 -20 6 180 Q> + <.PortSym 50 20 7 180 Q_> + + <.ID 20 44 Y "1=Clk_Delay=1e-10=Clock Delay (sec)=" "1=Set_Delay=1e-10=Set Delay (sec)=" "1=Reset_Delay=1e-10=Reset Delay (sec)=" "1=IC=0=Output Initial State=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)="> + + + + + +SR Flip-Flop +XSPICE Based + + +.Def:Digital_XSPICE_d_SR_FF _net5 _net6 _net0 _net3 _net4 _net2 _net1 Clk_Delay="1e-10" Set_Delay="1e-10" Reset_Delay="1e-10" IC="0" Rise_Delay="1e-10" Fall_Delay="1e-10" +Sub:X1 _net5 _net6 _net0 _net3 _net4 _net2 _net1 gnd Type="d_srff_cir" +.Def:End + + + +* XSPICE d_srff Digital S-R Flip-Flop +* +.subckt d_srff d_s d_r d_c d_set d_reset d_q d_q_ clk_delay=1.0e-10 set_delay=1.0e-10 reset_delay=1.0e-10 ic=0 rise_delay=1.0e-10 fall_delay=1e-10 +* +ad1 d_s d_r d_c d_set d_reset d_q d_q_ flop1 +.model flop1 d_srff(clk_delay='clk_delay' set_delay='set_delay' reset_delay='reset_delay' ic='ic' rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends d_srff + +.SUBCKT Digital_XSPICE_d_SR_FF gnd _net5 _net6 _net0 _net3 _net4 _net2 _net1 Clk_Delay=1e-10 Set_Delay=1e-10 Reset_Delay=1e-10 IC=0 Rise_Delay=1e-10 Fall_Delay=1e-10 +X1 _net5 _net6 _net0 _net3 _net4 _net2 _net1 d_srff CLK_DELAY=CLK_DELAY SET_DELAY=SET_DELAY RESET_DELAY=RESET_DELAY IC=IC RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + + + + + + + + + + <.PortSym -50 -20 1 0 S> + <.PortSym -50 20 2 0 R> + + + + + <.ID 20 44 Y "1=Clk_Delay=1e-10=Clock Delay (sec)=" "1=Set_Delay=1e-10=Set Delay (sec)=" "1=Reset_Delay=1e-10=Reset Delay (sec)=" "1=IC=0=Output Initial State=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)="> + + + + <.PortSym -50 0 3 0 C> + <.PortSym 0 -60 4 0 Set> + <.PortSym 0 60 5 0 Reset> + <.PortSym 50 -20 6 180 Q> + <.PortSym 50 20 7 180 Q_> + + + + + + +Digital Divider +50/50 Duty Requires +High-Cycles=(Div-Factor)/2 +XSPICE Based + + +.Def:Digital_XSPICE_d_Divider _net0 _net1 Div_Factor="2" High_Cycles="1" I_Count="0" Rise_Delay="1e-10" Fall_Delay="1e-10" +Sub:X1 _net0 _net1 gnd Type="d_divider_cir" +.Def:End + + + +**** XSPICE digital divider d_fdiv **** +* +* d_fin - digital input +* d_fout - digital output +* +.subckt dig_div d_fin d_fout div_factor=2 high_cycles=1 i_count=0 rise_delay=1e-10 fall_delay=1e-10) +* +adiv1 d_fin d_fout divider +* +.model divider d_fdiv(div_factor='div_factor' high_cycles='high_cycles' i_count='i_count' rise_delay='rise_delay' fall_delay='fall_delay') +* +.ends dig_div + +.SUBCKT Digital_XSPICE_d_Divider gnd _net0 _net1 Div_Factor=2 High_Cycles=1 I_Count=0 Rise_Delay=1e-10 Fall_Delay=1e-10 +X1 _net0 _net1 dig_div DIV_FACTOR=DIV_FACTOR HIGH_CYCLES=HIGH_CYCLES I_COUNT=I_COUNT RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY +.ENDS + + + + + + <.PortSym -50 0 1 0 IN> + <.PortSym 50 0 2 180 OUT> + + + + + + <.ID -20 24 DIV "1=Div_Factor=2=Division Ratio=" "1=High_Cycles=1=Number of high clock cycles=" "1=I_Count=0=Initial count value=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)="> + + diff --git a/library/qucs.blacklist b/library/qucs.blacklist index e179ded8..9261e7bf 100644 --- a/library/qucs.blacklist +++ b/library/qucs.blacklist @@ -13,3 +13,5 @@ VoltageReferences.lib PWM_Controller.lib MixerIC.lib SPICE_TLine.lib +Digital_AUX.lib +Digital_XSPICE.lib diff --git a/library/xyce.blacklist b/library/xyce.blacklist index 536dfbeb..39a210d0 100644 --- a/library/xyce.blacklist +++ b/library/xyce.blacklist @@ -4,3 +4,5 @@ PWM_Controller.lib Digital_CD.lib Digital_HC.lib Digital_LV.lib +Digital_AUX.lib +Digital_XSPICE.lib