Phase Lock Loop (PLL) Simulations

[tomhajjar]

Updated 1/08/25

Major update. The new capabilities of the "SPICE netlist" device which now allows the "Create Library..." Utility to create Libraries with Parameter Passing. All subcircuits have been converted from Spice Library to Spice netlist.

Project investigating the use of Qucs-S/ngspice for PLL simulations. The project uses PSpice 74HC digital devices which are based on XSPICE. Rules for using XSPICE digital devices apply.

PSpice digital components require .Param vcc=xx and set ngbehavior psa. All nodes are "digital" unless a DAC bridge is used or a connection is made to a "analog" device or resistor which initiates an "Auto-Bridge". I made 1/4/8 ADC-DAC Bridges and resistor packs to speed making schematics and add "digital" and "analog" interfaces between component types.

Plotting of voltages at "Digital" nodes requires using the "Plot Vs." option. Both "Digital "and "Analog" data can be plotted on the same Graph.

Simulations are faster if minimal Auto-Bridges are initiated but for typical circuits speed isn't an issue. No provision has been made to pass parameters to the PSpice devices. I haven't tried making subcircuits to implement the "LTspice" method of plotting digital timing diagrams. Just using equations as shown in the examples.

A second PLL project using XSPICE subcircuits is also available. #1131

PLL_CMOS_prj.zip