From bbf656d6a3d7fd9154d97e9398ad309e0a1d18d5 Mon Sep 17 00:00:00 2001 From: Matheus Cavalcante Date: Fri, 12 Feb 2021 09:39:08 +0100 Subject: [PATCH] [Changelog] Update CHANGELOG --- CHANGELOG.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 27d45c454..c1d12b2cb 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Hardware support for: - Vector single-width integer divide instructions (vdivu, vdiv, vremu, vrem) + - Vector integer comparison instructions (vmseq, vmsne, vmsltu, vmslt, vmsleu, vmsle, vmsgtu, vmsgt) - Runtime measurement functions - Consistent mode which orders scalar and vector loads/stores. - Conservative ordering without address comparison @@ -18,6 +19,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ### Fixed - Ariane's accelerator dispatcher module was rewritten, fixing a bug where instructions would get skipped. +- The Vector Store unit takes the EEW of the source vector register into account to shuffle the elements before writing them to memory. + +### Changed + +- Vector mask instructions (vmand, vmnand, vmandnot, vmxor, vmor, vmnor, vmornot, vmxnor) no longer require the non-compliant constraint that the vector length is divisible by eight. ## 0.4.0 - 2020-02-04