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top.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 00:32:05 January 29, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# top_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7064STC44-10"
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:32:05 JANUARY 29, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD TTL
set_location_assignment PIN_35 -to DIL_1
set_location_assignment PIN_42 -to DIL_2
set_location_assignment PIN_37 -to DIL_1_GCK
set_location_assignment PIN_40 -to DIL_2_GCK
set_location_assignment PIN_43 -to DIL_3
set_location_assignment PIN_44 -to DIL_4
set_location_assignment PIN_2 -to DIL_5
set_location_assignment PIN_3 -to DIL_6
set_location_assignment PIN_5 -to DIL_7
set_location_assignment PIN_8 -to DIL_8
set_location_assignment PIN_11 -to DIL_9
set_location_assignment PIN_12 -to DIL_10
set_location_assignment PIN_13 -to DIL_11
set_location_assignment PIN_14 -to DIL_12
set_location_assignment PIN_15 -to DIL_13
set_location_assignment PIN_18 -to DIL_15
set_location_assignment PIN_19 -to DIL_16
set_location_assignment PIN_20 -to DIL_17
set_location_assignment PIN_21 -to DIL_18
set_location_assignment PIN_22 -to DIL_19
set_location_assignment PIN_23 -to DIL_20
set_location_assignment PIN_25 -to DIL_21
set_location_assignment PIN_28 -to DIL_22
set_location_assignment PIN_31 -to DIL_23
set_location_assignment PIN_27 -to DIL_24
set_location_assignment PIN_30 -to DIL_25
set_location_assignment PIN_33 -to DIL_26
set_location_assignment PIN_34 -to DIL_27
set_location_assignment PIN_6 -to _PGND1
set_location_assignment PIN_10 -to _PGND2
set_location_assignment PIN_38 -to _IGND1
set_location_assignment PIN_39 -to _IGND2
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name SDC_FILE top.sdc
set_global_assignment -name TEXT_FILE readme.txt