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FP2 - Support for USB expansion port #21

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brockauly opened this issue Nov 29, 2024 · 5 comments
Open

FP2 - Support for USB expansion port #21

brockauly opened this issue Nov 29, 2024 · 5 comments

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@brockauly
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The Fairphone 2 has an USB expansion port behind the back cover, near the battery (found very few info, pinout here ).
It is not supported yet in the kernel (nothing is detected when I plug a peripheral).

What I tried

I have tried to modify the device tree, recompile the kernel and flash it but I cannot get it to work.
My fork is available here. I went from the branch qcom-msm8974-6.11.y and created a branch qcom-msm8974-6.11-wip where I added two tags (v6.11.5-msm8974 and v6.11.6-msm8974) to test my changes.
I then updated the APKBUILD of linux-postmarketos-qcom-msm8974 to retrieve the tar from my fork with my tag, then used pmbootstrap build --force linux-postmarketos-qcom-msm8974, then install & flash.
My modifications are correctly applied to the kernel, but the USB still doesn't work, so I suppose my modifications are wrong :

In /arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts

&usb {
	status = "okay";

	phys = <&usb_hs1_phy>, <&usb_hs2_phy>;
	phy-select = <&tcsr 0xb000 0>;
	extcon = <&smbb>, <&usb_id>;
	vbus-supply = <&chg_otg>;

	hnp-disable;
	srp-disable;
	adp-disable;
};

&usb_hs1_phy {
	status = "okay";

	v1p8-supply = <&pm8941_l6>;
	v3p3-supply = <&pm8941_l24>;

	extcon = <&smbb>;
	qcom,init-seq = /bits/ 8 <0x1 0x64>;
};

&usb_hs2_phy {
	status = "okay";

	v1p8-supply = <&pm8941_l6>;
	v3p3-supply = <&pm8941_l24>;

	extcon = <&smbb>;
	qcom,init-seq = /bits/ 8 <0x1 0x64>;
};

Have you already tried to modify this, or do you have any insight about what I am doing wrong ?

@brockauly
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I have also tried to enable only the second usb_phy, without success :

&usb {
	status = "okay";

	phys = <&usb_hs2_phy>;
	phy-select = <&tcsr 0xb000 0>;
	extcon = <&smbb>, <&usb_id>;
	vbus-supply = <&chg_otg>;

	hnp-disable;
	srp-disable;
	adp-disable;
};

&usb_hs2_phy {
	status = "okay";

	v1p8-supply = <&pm8941_l6>;
	v3p3-supply = <&pm8941_l24>;

	extcon = <&smbb>;
	qcom,init-seq = /bits/ 8 <0x1 0x64>;
};

@z3ntu
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z3ntu commented Nov 30, 2024

I've also looked into this at some point, but unfortunately I didn't have any hardware to test (or rather, the soldered-on USB-A port didn't even work with downstream kernel).

As far as I know, it should just be configuring the second USB port in dts, similar to what you've done and then it should work. But I don't think you can copy paste the properties from the primary USB node since they're connected differently and e.g. smbb shouldn't do much with the 2nd USB port.

Downstream commit: FairphoneMirrors/android_kernel_fairphone_msm8974@dfa0245

Maybe also relevant, the one pin for charging goes to smbb "DC" input, unlike the main USB connector which goes to the "USB" input of smbb.

But otherwise, the pogo pins directly connect to the SoC for the USB HS2 interface, main USB connector goes to HS1.

From SoC side the ID pin for HS2 is pulled to ground, so the USB OTG stuff can't work there, you probably need to force it to host mode.

@brockauly
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I have also tried to enable only the second usb_phy, without success :

Actually I managed to have the 2nd port ONLY by updating phy-select = <&tcsr 0xb000 1>; to select the other phy.
But in that case the main USB doesn't work anymore, obviously.

I can't find a way to enable both at the same time. Should I define a second USB controller to have one for each phy as in here ? In that case, how can I find the address of that second controller ? Can it be the same one ? I tried that without success.

Or is there a way to enable both phys with only one controller ? If yes, do you know how ?

@z3ntu
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z3ntu commented Dec 2, 2024

Looking at upstream dts I don't see any board currently using two phys in one controller, only qcom-apq8074-dragonboard.dts but that's only using the 2nd.

But from some commit message I'm pretty certain there's only one USB controller but with two PHYs.

I'd actually be curious now how downstream does this. I'll try asking around.

@z3ntu
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z3ntu commented Dec 6, 2024

Some copy paste from IRC:

(me) Do you know how msm8974 does it with the one USB controller and two PHYs? Can you enable both USB "ports" and make them functional at the same time? That seems to work downstream (or at least haven't heard anything different). At least upstream I don't see both phys being enabled at the same time
(me) E.g. on Fairphone 2 the main USB HS1 is connected to the micro USB connector on the phone, while USB HS2 is connected to some pogo pins on the back, and to my knowledge both work, not 100% sure at the same time but at least it's dynamically switching at the very least.

i think 8974 has a chipidea host and a dwc3 host

are they independent ports? or just two connectors on the same usb interface? the cases of one controller multiple ports i've seen has all been host-only

(me) I believe they function as separate ports at the same time, so you can connect something to the secondary one if you add a USB-A port to the logo pins and use the micro USB primary at the same time
(me) Schematics wise it's USB_HS1 pins on the SoC to one and USB_HS2 pins to the other
(me) There's also some more details about this connector at https://github.com/dirkvl/FairPhone/tree/master/Electronics but also doesn't say much more

host = controller
phy is a fancy adc/dac

I think it uses CI and dwc3 at the same time. At least on db8074 only some of the ports work.
I didn't have time for that :-(

there is a register in TCSR to switch between dwc3 and chipidea, or something along those lines: https://github.com/msm8916-mainline/lk2nd/blob/1b7174a47f7a497c02f04e5951548cc685143dde/target/msm8974/init.c#L823, not sure what the bits do exactly
I’d expect this works only if you use dwc3 for main USB and chipidea for the second (or possibly the other way around)
So you’d need to make the dwc3 work first

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