POR circuitry

[babusid]

We're having weird issues with behavior on chip reset being different than behavior on power cycle. This could be caused by chips coming on at different points in the voltage ramp after power cycle (ie. STM comes online sooner than some peripheral chips, and immediate initializations fail as a result). Including POR circuitry on the leader board would ensure that the STM only starts executing instructions once we're past a certain voltage threshold to ensure that program execution begins after all chips are on.