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axi_timer_and_interrupts.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="40" Path="C:/Zynq_Book/axi_timer_and_interrupts/axi_timer_and_interrupts.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ecd2a00a91b04602858685ccf01c43a1"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val="digilentinc.com:zybo:part0:1.0"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
</Configuration>
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<File Path="$PSRCDIR/sources_1/bd/zynq_interrupt_system_3_gpios/zynq_interrupt_system_3_gpios.bd">
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<Attr Name="UsedIn" Val="synthesis"/>
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</CompFileExtendedInfo>
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</File>
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</File>
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<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_wrapper"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="zynq_interrupt_system_3_gpios_axi_gpio_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/zynq_interrupt_system_3_gpios_axi_gpio_1_0">
<Config>
<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_axi_gpio_1_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="zynq_interrupt_system_3_gpios_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/zynq_interrupt_system_3_gpios_axi_gpio_0_0">
<Config>
<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_axi_gpio_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="zynq_interrupt_system_3_gpios_axi_timer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/zynq_interrupt_system_3_gpios_axi_timer_0_0">
<Config>
<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_axi_timer_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="zynq_interrupt_system_3_gpios_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/zynq_interrupt_system_3_gpios_xbar_0">
<Config>
<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="zynq_interrupt_system_3_gpios_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/zynq_interrupt_system_3_gpios_auto_pc_0">
<Config>
<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_auto_pc_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="zynq_interrupt_system_3_gpios_rst_ps7_0_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/zynq_interrupt_system_3_gpios_rst_ps7_0_100M_0">
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<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_rst_ps7_0_100M_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="zynq_interrupt_system_3_gpios_axi_gpio_2_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/zynq_interrupt_system_3_gpios_axi_gpio_2_0">
<Config>
<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_axi_gpio_2_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="zynq_interrupt_system_3_gpios_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/zynq_interrupt_system_3_gpios_processing_system7_0_0">
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<Option Name="TopModule" Val="zynq_interrupt_system_3_gpios_processing_system7_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
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<Option Name="CompiledLib" Val="0"/>
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<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
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<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="zynq_interrupt_system_3_gpios_axi_gpio_1_0_synth_1" Type="Ft3:Synth" SrcSet="zynq_interrupt_system_3_gpios_axi_gpio_1_0" Part="xc7z010clg400-1" ConstrsSet="zynq_interrupt_system_3_gpios_axi_gpio_1_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/zynq_interrupt_system_3_gpios_axi_gpio_1_0_synth_1" IncludeInArchive="true">
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