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Copy path3324-Add-support-for-ATmega1284p-AVR-processor-spec.patch
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3324-Add-support-for-ATmega1284p-AVR-processor-spec.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Matt Ranostay <[email protected]>
Date: Tue, 10 Aug 2021 20:05:21 -0700
Subject: [PATCH] 3324: Add support for ATmega1284p AVR processor spec
---
.../Processors/Atmel/certification.manifest | 1 +
.../Atmel/data/languages/atmega1284p.pspec | 171 ++++++++++++++++++
.../Atmel/data/languages/avr8.ldefs | 15 ++
3 files changed, 187 insertions(+)
create mode 100644 Ghidra/Processors/Atmel/data/languages/atmega1284p.pspec
diff --git a/Ghidra/Processors/Atmel/certification.manifest b/Ghidra/Processors/Atmel/certification.manifest
index 00ddbbf807..30116f230b 100644
--- a/Ghidra/Processors/Atmel/certification.manifest
+++ b/Ghidra/Processors/Atmel/certification.manifest
@@ -1,6 +1,7 @@
##VERSION: 2.0
Module.manifest||GHIDRA||||END|
data/languages/atmega256.pspec||GHIDRA||||END|
+data/languages/atmega1284p.pspec||GHIDRA||||END|
data/languages/avr32.opinion||GHIDRA||||END|
data/languages/avr32a.cspec||GHIDRA||||END|
data/languages/avr32a.ldefs||GHIDRA||||END|
diff --git a/Ghidra/Processors/Atmel/data/languages/atmega1284p.pspec b/Ghidra/Processors/Atmel/data/languages/atmega1284p.pspec
new file mode 100644
index 0000000000..e908b484fb
--- /dev/null
+++ b/Ghidra/Processors/Atmel/data/languages/atmega1284p.pspec
@@ -0,0 +1,171 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<processor_spec>
+
+ <programcounter register="PC"/>
+ <data_space space="mem"/>
+
+ <volatile outputop="write_volatile" inputop="read_volatile">
+ <range space="mem" first="0x20" last="0x57"/>
+ <range space="mem" first="0x5B" last="0xff"/>
+ </volatile>
+
+ <default_symbols>
+
+ <symbol name="RESET" address="code:0x0000" entry="true"/>
+ <symbol name="INT0" address="code:0x0002" entry="true"/>
+ <symbol name="INT1" address="code:0x0004" entry="true"/>
+ <symbol name="INT2" address="code:0x0006" entry="true"/>
+ <symbol name="PCINT0" address="code:0x0008" entry="true"/>
+ <symbol name="PCINT1" address="code:0x000A" entry="true"/>
+ <symbol name="PCINT2" address="code:0x000C" entry="true"/>
+ <symbol name="PCINT3" address="code:0x000E" entry="true"/>
+ <symbol name="WDT" address="code:0x0010" entry="true"/>
+ <symbol name="TIMER2_COMPA" address="code:0x0012" entry="true"/>
+ <symbol name="TIMER2_COMPB" address="code:0x0014" entry="true"/>
+ <symbol name="TIMER2_OVF" address="code:0x0016" entry="true"/>
+ <symbol name="TIMER1_CAPT" address="code:0x0018" entry="true"/>
+ <symbol name="TIMER1_COMPA" address="code:0x001A" entry="true"/>
+ <symbol name="TIMER1_COMPB" address="code:0x001C" entry="true"/>
+ <symbol name="TIMER1_OVF" address="code:0x001E" entry="true"/>
+ <symbol name="TIMER0_COMPA" address="code:0x0020" entry="true"/>
+ <symbol name="TIMER0_COMPB" address="code:0x0022" entry="true"/>
+ <symbol name="TIMER0_OVF" address="code:0x0024" entry="true"/>
+ <symbol name="SPI_STC" address="code:0x0026" entry="true"/>
+ <symbol name="USART0_RX" address="code:0x0028" entry="true"/>
+ <symbol name="USART0_UDRE" address="code:0x002A" entry="true"/>
+ <symbol name="USART0_TX" address="code:0x002C" entry="true"/>
+ <symbol name="ANALOG_COMP" address="code:0x002E" entry="true"/>
+ <symbol name="ADC" address="code:0x0030" entry="true"/>
+ <symbol name="EE_READY" address="code:0x0032" entry="true"/>
+ <symbol name="TWI" address="code:0x0034" entry="true"/>
+ <symbol name="SPM_READY" address="code:0x0036" entry="true"/>
+ <symbol name="USART1_RX" address="code:0x0038" entry="true"/>
+ <symbol name="USART1_UDRE" address="code:0x003A" entry="true"/>
+ <symbol name="USART1_TX" address="code:0x003C" entry="true"/>
+ <symbol name="TIMER3_CAPT" address="code:0x003E" entry="true"/>
+ <symbol name="TIMER3_COMPA" address="code:0x0040" entry="true"/>
+ <symbol name="TIMER3_COMPB" address="code:0x0042" entry="true"/>
+ <symbol name="TIMER3_OVF" address="code:0x0044" entry="true"/>
+
+ <symbol name="UDR1" address="mem:0xCE"/>
+ <symbol name="UBRR1H" address="mem:0xCD"/>
+ <symbol name="UBRR1L" address="mem:0xCC"/>
+ <symbol name="UCSR1C" address="mem:0xCA"/>
+ <symbol name="UCSR1B" address="mem:0xC9"/>
+ <symbol name="UCSR1A" address="mem:0xC8"/>
+ <symbol name="UDR0" address="mem:0xC6"/>
+ <symbol name="UBRR0H" address="mem:0xC5"/>
+ <symbol name="UBRR0L" address="mem:0xC4"/>
+ <symbol name="UCSR0C" address="mem:0xC2"/>
+ <symbol name="UCSR0B" address="mem:0xC1"/>
+ <symbol name="UCSR0A" address="mem:0xC0"/>
+ <symbol name="TWAMR" address="mem:0xBD"/>
+ <symbol name="TWCR" address="mem:0xBC"/>
+ <symbol name="TWDR" address="mem:0xBB"/>
+ <symbol name="TWAR" address="mem:0xBA"/>
+ <symbol name="TWSR" address="mem:0xB9"/>
+ <symbol name="TWBR" address="mem:0xB8"/>
+ <symbol name="ASSR" address="mem:0xB6"/>
+ <symbol name="OCR2B" address="mem:0xB4"/>
+ <symbol name="OCR2A" address="mem:0xB3"/>
+ <symbol name="TCCR2B" address="mem:0xB1"/>
+ <symbol name="TCCR2A" address="mem:0xB0"/>
+ <symbol name="OCR3BH" address="mem:0x9B"/>
+ <symbol name="OCR3BL" address="mem:0x9A"/>
+ <symbol name="OCR3AH" address="mem:0x99"/>
+ <symbol name="OCR3AL" address="mem:0x98"/>
+ <symbol name="ICR3H" address="mem:0x97"/>
+ <symbol name="ICR3L" address="mem:0x96"/>
+ <symbol name="TCNT3H" address="mem:0x95"/>
+ <symbol name="TCNT3L" address="mem:0x94"/>
+ <symbol name="TCCR3C" address="mem:0x92"/>
+ <symbol name="TCCR3B" address="mem:0x91"/>
+ <symbol name="TCCR3A" address="mem:0x90"/>
+ <symbol name="OCR1BH" address="mem:0x8B"/>
+ <symbol name="OCR1BL" address="mem:0x8A"/>
+ <symbol name="OCR1AH" address="mem:0x89"/>
+ <symbol name="OCR1AL" address="mem:0x88"/>
+ <symbol name="ICR1H" address="mem:0x87"/>
+ <symbol name="ICR1L" address="mem:0x86"/>
+ <symbol name="TCNT1H" address="mem:0x85"/>
+ <symbol name="TCNT1L" address="mem:0x84"/>
+ <symbol name="TCCR1C" address="mem:0x82"/>
+ <symbol name="TCCR1B" address="mem:0x81"/>
+ <symbol name="TCCR1A" address="mem:0x80"/>
+ <symbol name="DIDR1" address="mem:0x7F"/>
+ <symbol name="DIDR0" address="mem:0x7E"/>
+ <symbol name="ADMUX" address="mem:0x7C"/>
+ <symbol name="ADCSRB" address="mem:0x7B"/>
+ <symbol name="ADCSRA" address="mem:0x7A"/>
+ <symbol name="ADCH" address="mem:0x79"/>
+ <symbol name="ADCL" address="mem:0x78"/>
+ <symbol name="PCMSK3" address="mem:0x73"/>
+ <symbol name="TIMSK3" address="mem:0x71"/>
+ <symbol name="TIMSK2" address="mem:0x70"/>
+ <symbol name="TIMSK1" address="mem:0x6F"/>
+ <symbol name="TIMSK0" address="mem:0x6E"/>
+ <symbol name="PCMSK2" address="mem:0x6D"/>
+ <symbol name="PCMSK1" address="mem:0x6C"/>
+ <symbol name="PCMSK0" address="mem:0x6B"/>
+ <symbol name="EICRA" address="mem:0x69"/>
+ <symbol name="PCICR" address="mem:0x68"/>
+ <symbol name="OSCCAL" address="mem:0x66"/>
+ <symbol name="PRR1" address="mem:0x65"/>
+ <symbol name="PRR0" address="mem:0x64"/>
+ <symbol name="CLKPR" address="mem:0x61"/>
+ <symbol name="WDTCSR" address="mem:0x60"/>
+ <symbol name="SREG" address="mem:0x5F"/>
+ <symbol name="SPH" address="mem:0x5E"/>
+ <symbol name="SPL" address="mem:0x5D"/>
+ <symbol name="RAMPZ" address="mem:0x5B"/>
+ <symbol name="SPMCSR" address="mem:0x57"/>
+ <symbol name="MCUCR" address="mem:0x55"/>
+ <symbol name="MCUSR" address="mem:0x54"/>
+ <symbol name="SMCR" address="mem:0x53"/>
+ <symbol name="OCDR" address="mem:0x51"/>
+ <symbol name="ACSR" address="mem:0x50"/>
+ <symbol name="SPDR" address="mem:0x4E"/>
+ <symbol name="SPSR" address="mem:0x4D"/>
+ <symbol name="SPCR" address="mem:0x4C"/>
+ <symbol name="GPIOR2" address="mem:0x4B"/>
+ <symbol name="GPIOR1" address="mem:0x4A"/>
+ <symbol name="OCR0B" address="mem:0x48"/>
+ <symbol name="OCR0A" address="mem:0x47"/>
+ <symbol name="TCCR0B" address="mem:0x45"/>
+ <symbol name="TCCR0A" address="mem:0x44"/>
+ <symbol name="GTCCR" address="mem:0x43"/>
+ <symbol name="EEARH" address="mem:0x42"/>
+ <symbol name="EEARL" address="mem:0x41"/>
+ <symbol name="EEDR" address="mem:0x40"/>
+ <symbol name="EECR" address="mem:0x3F"/>
+ <symbol name="GPIOR0" address="mem:0x3E"/>
+ <symbol name="EIMSK" address="mem:0x3D"/>
+ <symbol name="EIFR" address="mem:0x3C"/>
+ <symbol name="PCIFR" address="mem:0x3B"/>
+ <symbol name="TIFR3" address="mem:0x38"/>
+ <symbol name="TIFR2" address="mem:0x37"/>
+ <symbol name="TIFR1" address="mem:0x36"/>
+ <symbol name="TIFR0" address="mem:0x35"/>
+ <symbol name="PORTD" address="mem:0x2B"/>
+ <symbol name="DDRD" address="mem:0x2A"/>
+ <symbol name="PIND" address="mem:0x29"/>
+ <symbol name="PORTC" address="mem:0x28"/>
+ <symbol name="DDRC" address="mem:0x27"/>
+ <symbol name="PINC" address="mem:0x26"/>
+ <symbol name="PORTB" address="mem:0x25"/>
+ <symbol name="DDRB" address="mem:0x24"/>
+ <symbol name="PINB" address="mem:0x23"/>
+ <symbol name="PORTA" address="mem:0x22"/>
+ <symbol name="DDRA" address="mem:0x21"/>
+ <symbol name="PINA" address="mem:0x20"/>
+
+ </default_symbols>
+
+ <default_memory_blocks>
+ <memory_block name="regalias" start_address="mem:0x00" length="0x20" initialized="false"/>
+ <memory_block name="iospace" start_address="mem:0x20" length="0xdf" initialized="false"/>
+ <memory_block name="data" start_address="mem:0x100" length="0x3fff" initialized="false"/>
+ </default_memory_blocks>
+
+</processor_spec>
diff --git a/Ghidra/Processors/Atmel/data/languages/avr8.ldefs b/Ghidra/Processors/Atmel/data/languages/avr8.ldefs
index 35a6be1fea..eeadec0f58 100644
--- a/Ghidra/Processors/Atmel/data/languages/avr8.ldefs
+++ b/Ghidra/Processors/Atmel/data/languages/avr8.ldefs
@@ -49,6 +49,21 @@
<external_name tool="gnu" name="avr:6"/>
<external_name tool="IDA-PRO" name="avr"/>
</language>
+
+ <language processor="AVR8"
+ endian="little"
+ size="24"
+ variant="atmega1284p"
+ version="1.0"
+ slafile="avr8eind.sla"
+ processorspec="atmega1284p.pspec"
+ manualindexfile="../manuals/AVR8.idx"
+ id="avr8:LE:16:atmega1284p">
+ <description>AVR8 for an Atmega 1248p</description>
+ <compiler name="gcc" spec="avr8egcc.cspec" id="gcc"/>
+ <external_name tool="gnu" name="avr:6"/>
+ <external_name tool="IDA-PRO" name="avr"/>
+ </language>
<language processor="AVR8"
endian="little"
--
2.45.1