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Copy path2617-Support-CPU32-version-of-the-68000-instruction-.patch
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2617-Support-CPU32-version-of-the-68000-instruction-.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: NSFW <[email protected]>
Date: Mon, 4 Jan 2021 01:52:15 -0800
Subject: [PATCH] 2617: Support CPU32 version of the 68000 instruction set
CPU32
Updated certification manifest.
---
.../Processors/68000/certification.manifest | 1 +
.../68000/data/languages/68000.ldefs | 13 ++
.../68000/data/languages/68000.sinc | 149 ++++++++++++++++++
.../68000/data/languages/CPU32.slaspec | 6 +
4 files changed, 169 insertions(+)
create mode 100644 Ghidra/Processors/68000/data/languages/CPU32.slaspec
diff --git a/Ghidra/Processors/68000/certification.manifest b/Ghidra/Processors/68000/certification.manifest
index 55d58490e3..caf51979e7 100644
--- a/Ghidra/Processors/68000/certification.manifest
+++ b/Ghidra/Processors/68000/certification.manifest
@@ -12,6 +12,7 @@ data/languages/68020.slaspec||GHIDRA||reviewed||END|
data/languages/68030.slaspec||GHIDRA||||END|
data/languages/68040.slaspec||GHIDRA||||END|
data/languages/coldfire.slaspec||GHIDRA||||END|
+data/languages/CPU32.slaspec||GHIDRA||||END|
data/manuals/68000.idx||GHIDRA||||END|
data/patterns/68000_patterns.xml||GHIDRA||||END|
data/patterns/patternconstraints.xml||GHIDRA||||END|
diff --git a/Ghidra/Processors/68000/data/languages/68000.ldefs b/Ghidra/Processors/68000/data/languages/68000.ldefs
index 5115f2d878..4b9135c686 100644
--- a/Ghidra/Processors/68000/data/languages/68000.ldefs
+++ b/Ghidra/Processors/68000/data/languages/68000.ldefs
@@ -73,4 +73,17 @@
<external_name tool="qemu" name="qemu-m68k"/>
<external_name tool="qemu_system" name="qemu-system-m68k"/>
</language>
+ <language processor="68000"
+ endian="big"
+ size="32"
+ variant="CPU32"
+ version="1.1"
+ slafile="CPU32.sla"
+ processorspec="68000.pspec"
+ manualindexfile="../manuals/68000.idx"
+ id="68000:BE:32:CPU32">
+ <description>Motorola 32-bit CPU32</description>
+ <compiler name="default" spec="68000.cspec" id="default"/>
+ <external_name tool="IDA-PRO" name="CPU32"/>
+ </language>
</language_definitions>
diff --git a/Ghidra/Processors/68000/data/languages/68000.sinc b/Ghidra/Processors/68000/data/languages/68000.sinc
index 9ad6a66119..f23034c269 100644
--- a/Ghidra/Processors/68000/data/languages/68000.sinc
+++ b/Ghidra/Processors/68000/data/languages/68000.sinc
@@ -59,6 +59,10 @@ define register offset=0x746 size=10 [ FP7 ];
@define DAT_DIR_CTL_ADDR_MODES2 "(mode2=0 | mode2=2 | mode2=5 | mode2=6 | mode=7)" # Data direct and control addressing modes
@define CTL_ADDR_MODES2 "(mode2=2 | mode2=5 | mode2=6 | mode2=7)" # Control addressing modes
+@ifdef CPU32
+@define TBL_ADDR_MODES "(tbl_mode=2 | tbl_mode=4 | tbl_mode=5 | tbl_mode=6 | tbl_mode=7)" # Addressing modes for tblxx instructions
+@endif
+
# Floating-point condition code bits within FPSR
@define N_FP "FPSR[27,1]"
@define Z_FP "FPSR[26,1]"
@@ -173,7 +177,31 @@ define token extword (16)
reg12xwu = (12,15)
reg12xwl = (12,15)
@endif
+@ifdef CPU32 # Data register interpolation fields for TBL instructions.
+ tbl_dr_size = (6,7)
+ tbl_dr_round = (10,10)
+ tbl_dr_sign = (11,11)
+ tbl_dr_reg = (0,2)
+@endif
+;
+
+@ifdef CPU32
+# The TBLxx instructions are two 16-bit tokens optionally followed by a disp16 token.
+# The presence of the disp16 token is governed by bits in the first token.
+# Sleigh's ... operator follows the second token, but needs the bits from the first.
+# To work around that, a single 32-bit token is used in place of the standard tokens.
+define token tbl_instrA(32)
+ tbl_regan=(16,18)
+ tbl_mode=(19,21)
+ tbl_op37=(19,23)
+ tbl_op67=(22,23)
+ tbl_opbig=(24,31)
+ tbl_size=(6,7)
+ tbl_round=(10,10)
+ tbl_sign=(11,11)
+ tbl_regxdn=(12,14)
;
+@endif
define token extword2 (16)
regda2 = (12,15)
@@ -305,7 +333,12 @@ define context contextreg
extGUARD = (14,14) # guard for saving off modes before starting instructions
;
+@ifdef CPU32
+attach variables [ regdn regxdn reg9dn regdr regdq regsdn regdu regdc regdu2 regdc2 tbl_regxdn tbl_dr_reg ] [ D0 D1 D2 D3 D4 D5 D6 D7 ];
+@else
attach variables [ regdn regxdn reg9dn regdr regdq regsdn regdu regdc regdu2 regdc2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 ];
+@endif
+
attach variables [ fldoffreg fldwdreg f_reg fcnt fkfacreg fldynreg ] [ D0 D1 D2 D3 D4 D5 D6 D7 ];
attach variables [ regdnw regxdnw reg9dnw regsdnw regduw regdcw regdu2w regdc2w ] [ D0w D1w D2w D3w D4w D5w D6w D7w ];
attach variables [ regdnb reg9dnb regsdnb regdub regdcb ] [ D0b D1b D2b D3b D4b D5b D6b D7b ];
@@ -579,11 +612,13 @@ Tyb: regdnb is rmbit=0 & regdnb { export regdnb; }
Txb: -(reg9an) is rmbit=1 & reg9an { reg9an = reg9an-1; export *:1 reg9an; }
Txb: reg9dnb is rmbit=0 & reg9dnb { export reg9dnb; }
+@ifndef CPU32
# Bit field parameters
f_off: fldoffdat is flddo=0 & fldoffdat { export *[const]:4 fldoffdat; }
f_off: fldoffreg is flddo=1 & fldoffreg { export fldoffreg; }
f_wd: fldwddat is flddw=0 & fldwddat { export *[const]:4 fldwddat; }
f_wd: fldwdreg is flddw=1 & fldwdreg { export fldwdreg; }
+@endif # CPU32
rreg: regxdn is da=0 & regxdn { export regxdn; }
rreg: regxan is da=1 & regxan { export regxan; }
@@ -1043,6 +1078,7 @@ with : extGUARD=1 {
local source = regdn; mask:4 = 1 << (const8 & 31); ZF = (source & mask) == 0; regdn = source & (~mask);
}
+@ifndef CPU32
:bfchg e2l{f_off:f_wd} is opbig=0xea & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
logflags();
tmp:4 = e2l;
@@ -1135,6 +1171,7 @@ with : extGUARD=1 {
getbitfield(tmp, f_off, f_wd);
resbitflags(tmp, f_wd-1);
}
+@endif # CPU32
define pcodeop breakpoint;
:bkpt "#"op02 is opbig=0x48 & op67=1 & op5=0 & op34=1 & op02 { breakpoint(); }
@@ -1196,6 +1233,8 @@ define pcodeop breakpoint;
}
@endif # COLDFIRE
+
+@ifndef CPU32
# TODO: Determine layout of a module descriptor
define pcodeop callm;
:callm const8,e2l is opbig=6 & op67=3 & $(CTL_ADDR_MODES); const8; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
@@ -1271,6 +1310,7 @@ define pcodeop callm;
ZF = 1;
NF = 0;
}
+@endif # CPU32
:chk.w eaw,reg9dnw is (op=4 & reg9dnw & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eaw {
build eaw;
@@ -1423,11 +1463,16 @@ cachetype: "both" is op67=3 { export 3:4; }
subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }
:cmpm.l (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=2 & op5=0 & op34=1 & regan { local tmp1=*:4 regan; regan=regan+4; local tmp2=*:4 reg9an; reg9an=reg9an+4;
subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }
+
+@ifndef CPU32
# cpBcc # need to know specific copressors use copcc1
# cpDBcc # use copcc2
# cpGEN
+# cpRESTORE
+# cpSAVE
# cpScc # use copcc2
# cpTRAPcc # use copcc2
+@endif # CPU32
:db^cc regdnw,addr16 is op=5 & cc & op67=3 & op5=0 & op34=1 & regdnw; addr16 {
if (cc) goto inst_next;
@@ -2020,6 +2065,7 @@ macro negResFlags(result) {
:ori const8,"CCR" is opbig=0 & op37=7 & op02=4; const8 { packflags(SR); SR=SR|zext(const8); unpackflags(SR); }
:ori const16,SR is SR; opbig=0x00 & d8base=0x7c; const16 { packflags(SR); SR=SR|const16; unpackflags(SR); }
+@ifndef CPU32
:pack Tyw,Txw,const16 is op=8 & op48=20 & Txw & Tyw & rmbit=0; const16 {
local value = (Tyw & 0x0F0F) + const16;
Txw = (Txw & 0xFF00) | ((value & 0x0F00) >> 4) | (value & 0x000F);
@@ -2030,6 +2076,7 @@ macro negResFlags(result) {
local result:2 = ((value & 0x0F00) >> 4) | (value & 0x000F);
Txb = result:1;
}
+@endif # CPU32
:pea eaptr is (opbig=0x48 & op67=1 & $(CTL_ADDR_MODES))... & eaptr { value:4 = eaptr; SP = SP-4; *SP = value; }
@@ -2187,9 +2234,11 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; }
:rtd const16 is opbig=0x4e & op37=14 & op02=4; const16 { PC = *SP; SP = SP + 4 + zext(const16); return [PC]; }
:rte is d16=0x4e73 { tmp:4 = 0; return [tmp]; }
+@ifndef CPU32
define pcodeop rtm;
:rtm regdn is opbig=0x06 & op37=24 & regdn { PC = rtm(regdn); return [PC]; }
:rtm regan is opbig=0x06 & op37=25 & regan { PC = rtm(regan); return [PC];}
+@endif # CPU32
:rtr is opbig=0x4e & op37=14 & op02=7 { SR = *SP; SP = SP+2; PC = *SP; SP = SP+4; unpackflags(SR); return [PC]; }
@@ -2210,6 +2259,14 @@ define pcodeop stop;
stop();
}
+@ifdef CPU32
+#TODO: implement interrupt mask → EBI; STOP
+:lpstop "#"^d16 is opbig=0xf8 & d8base=0x00; opbig=0x01 & d8base=0xC0; d16 { SR = d16; }
+
+#TODO: implement: if (background mode enabled) then enter Background Mode else Format/Vector offset → –(SSP); PC → –(SSP); SR → –(SSP); (Vector) → PC
+:bgnd is opbig=0x4A & d8base=0xFA { }
+@endif # CPU32
+
:sub.b eab,reg9dnb is (op=9 & reg9dnb & op68=0)... & eab { sub(eab, reg9dnb); }
:sub.w eaw,reg9dnw is (op=9 & reg9dnw & op68=1)... & eaw { sub(eaw, reg9dnw); }
:sub.l eal,reg9dn is (op=9 & reg9dn & op68=2)... & eal { sub(eal, reg9dn); }
@@ -2250,6 +2307,96 @@ define pcodeop stop;
:tas eab is (opbig=0x4a & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); resflags(eab); eab = eab | 0x80; }
@endif # COLDFIRE
+@ifdef CPU32
+
+# TODO: tbl_mode=4 and tbl_mode=5 constructors
+
+tbl_eal: (tbl_regan) is tbl_mode=2 & tbl_regan { export *:4 tbl_regan; }
+# tbl_eal: -(tbl_regan) is tbl_mode=4 & tbl_regan { tbl_regan = tbl_regan - 4; export *:4 tbl_regan; }
+# tbl_eal: (d16,tbl_regan) is tbl_mode=5 & tbl_regan; d16 { local tmp = tbl_regan + d16; export *:4 tmp; }
+tbl_eal: (extw) is tbl_mode=6 & tbl_regan; extw [ regtfan = tbl_regan; pcmode = 0; ] { build extw; export *:4 extw; }
+tbl_eal: (d16,PC) is PC & tbl_mode=7 & tbl_regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:4 tmp; }
+tbl_eal: (extw) is tbl_mode=7 & tbl_regan=3; extw [ pcmode=1; ] { build extw; export *:4 extw; }
+tbl_eal: (d16)".w" is tbl_mode=7 & tbl_regan=0; d16 { export *:4 d16; }
+tbl_eal: (d32)".l" is tbl_mode=7 & tbl_regan=1; d32 { export *:4 d32; }
+tbl_eal: "#"^d32 is tbl_mode=7 & tbl_regan=4; d32 { export *[const]:4 d32; }
+
+tbl_eaw: (tbl_regan) is tbl_mode=2 & tbl_regan { export *:2 tbl_regan; }
+# tbl_eaw: -(tbl_regan) is tbl_mode=4 & tbl_regan { tbl_regan = tbl_regan - 2; export *:2 tbl_regan; }
+# tbl_eaw: (d16,tbl_regan) is tbl_mode=5 & tbl_regan; d16 { local tmp = tbl_regan + d16; export *:2 tmp; }
+tbl_eaw: (extw) is tbl_mode=6 & tbl_regan; extw [ pcmode=0; regtfan=tbl_regan; ] { build extw; export *:2 extw; }
+tbl_eaw: (d16,PC) is PC & tbl_mode=7 & tbl_regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:2 tmp; }
+tbl_eaw: (extw) is tbl_mode=7 & tbl_regan=3; extw [ pcmode=1; ] { build extw; export *:2 extw; }
+tbl_eaw: (d16)".w" is tbl_mode=7 & tbl_regan=0; d16 { export *:2 d16; }
+tbl_eaw: (d32)".l" is tbl_mode=7 & tbl_regan=1; d32 { export *:2 d32; }
+tbl_eaw: "#"^d16 is tbl_mode=7 & tbl_regan=4; d16 { export *[const]:2 d16; }
+
+tbl_eab: (tbl_regan) is tbl_mode=2 & tbl_regan { export *:1 tbl_regan; }
+# tbl_eab: -(tbl_regan) is tbl_mode=4 & tbl_regan { tbl_regan = tbl_regan - 1; export *:1 tbl_regan; }
+# tbl_eab: (d16,tbl_regan) is tbl_mode=5 & tbl_regan; d16 { local tmp = tbl_regan + d16; export *:1 tmp; }
+tbl_eab: (extw) is tbl_mode=6 & tbl_regan; extw [ pcmode=0; regtfan=tbl_regan; ] { build extw; export *:1 extw; }
+tbl_eab: (d16,PC) is PC & tbl_mode=7 & tbl_regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:1 tmp; }
+tbl_eab: (extw) is tbl_mode=7 & tbl_regan=3; extw [ pcmode=1; ] { build extw; export *:1 extw; }
+tbl_eab: (d16)".w" is tbl_mode=7 & tbl_regan=0; d16 { export *:1 d16; }
+tbl_eab: (d32)".l" is tbl_mode=7 & tbl_regan=1; d32 { export *:1 d32; }
+tbl_eab: "#"^d8 is tbl_mode=7 & tbl_regan=4; d8 { export *[const]:1 d8; }
+
+tblsign: "u" is tbl_sign=0 { }
+tblsign: "s" is tbl_sign=1 { }
+
+tbldrsign: "u" is tbl_dr_sign=0 { }
+tbldrsign: "s" is tbl_dr_sign=1 { }
+
+define pcodeop tableLookup;
+
+# Rounded Table Lookup and Interpolate
+
+:tbl^tblsign^".b" tbl_eab,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=0 & tblsign & tbl_round=0 & tbl_regxdn) ... & tbl_eab
+ { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eab); }
+
+:tbl^tblsign^".w" tbl_eaw,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=1 & tblsign & tbl_round=0 & tbl_regxdn) ... & tbl_eaw
+ { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eaw); }
+
+:tbl^tblsign^".l" tbl_eal,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=2 & tblsign & tbl_round=0 & tbl_regxdn) ... & tbl_eal
+ { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eal); }
+
+# Unrounded Table Lookup and Interpolate
+
+:tbl^tblsign^"n.b" tbl_eab,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=0 & tblsign & tbl_round=1 & tbl_regxdn) ... & tbl_eab
+ { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eab); }
+
+:tbl^tblsign^"n.w" tbl_eaw,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=1 & tblsign & tbl_round=1 & tbl_regxdn) ... & tbl_eaw
+ { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eaw); }
+
+:tbl^tblsign^"n.l" tbl_eal,tbl_regxdn is (tbl_opbig=0xF8 & tbl_op67=0 & $(TBL_ADDR_MODES) & tbl_size=2 & tblsign & tbl_round=1 & tbl_regxdn) ... & tbl_eal
+ { tbl_regxdn = tableLookup(tbl_regxdn, tbl_eal); }
+
+define pcodeop interpolate;
+
+# Rounded Data Register Interpolate
+
+:tbl^tbldrsign^".b" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=0 & tbldrsign & tbl_dr_round=0 & tbl_dr_reg & regxdn
+ { regxdn = interpolate(regdn, tbl_dr_reg); }
+
+:tbl^tbldrsign^".w" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=1 & tbldrsign & tbl_dr_round=0 & tbl_dr_reg & regxdn
+ { regxdn = interpolate(regdn, tbl_dr_reg); }
+
+:tbl^tbldrsign^".l" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=2 & tbldrsign & tbl_dr_round=0 & tbl_dr_reg & regxdn
+ { regxdn = interpolate(regdn, tbl_dr_reg); }
+
+# Unrounded Data Register Interpolate
+
+:tbl^tbldrsign^"n.b" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=0 & tbldrsign & tbl_dr_round=1 & tbl_dr_reg & regxdn
+ { regxdn = interpolate(regdn, tbl_dr_reg); }
+
+:tbl^tbldrsign^"n.w" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=1 & tbldrsign & tbl_dr_round=1 & tbl_dr_reg & regxdn
+ { regxdn = interpolate(regdn, tbl_dr_reg); }
+
+:tbl^tbldrsign^"n.l" regdn:tbl_dr_reg,regxdn is opbig=0xF8 & op37=0 & mode=0 & regdn ; tbl_dr_size=2 & tbldrsign & tbl_dr_round=1 & tbl_dr_reg & regxdn
+ { regxdn = interpolate(regdn, tbl_dr_reg); }
+
+@endif # CPU32
+
:trap "#"^op03 is opbig=0x4e & op67=1 & op45=0 & op03 { vector:1 = op03; __m68k_trap(vector); }
:trap^cc is op=5 & cc & op37=31 & op02=4 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = inst_next; vector:1 = 7; __m68k_trap(vector); }
:trap^cc^".w" const16 is op=5 & cc & op37=31 & op02=2; const16 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = inst_next; __m68k_trapv(); }
@@ -2266,6 +2413,7 @@ define pcodeop stop;
:unlk regan is opbig=0x4e & op37=11 & regan { SP = regan; regan = *SP; SP = SP+4; }
+@ifndef CPU32
:unpk Tyw,Txw,const16 is op=8 & Txw & op48=24 & Tyw & rmbit=0; const16 {
Txw = (Txw & 0xF0F0) | ((((Tyw & 0x00F0) << 4) | (Tyw & 0x000F)) + const16);
}
@@ -2275,6 +2423,7 @@ define pcodeop stop;
source = (((source & 0x00F0) << 4) | (source & 0x000F)) + const16;
Txw = (Txw & 0xF0F0) | source;
}
+@endif # CPU32
# Floating Point Instructions
diff --git a/Ghidra/Processors/68000/data/languages/CPU32.slaspec b/Ghidra/Processors/68000/data/languages/CPU32.slaspec
new file mode 100644
index 0000000000..dc2c54ab6f
--- /dev/null
+++ b/Ghidra/Processors/68000/data/languages/CPU32.slaspec
@@ -0,0 +1,6 @@
+# Motorola's CPU32 processor
+
+@define CPU32 ""
+@define MC68332 ""
+
+@include "68000.sinc"
--
2.45.1