diff --git a/uboot/make_uboot.sh b/uboot/make_uboot.sh index 09a3704..faeaf13 100644 --- a/uboot/make_uboot.sh +++ b/uboot/make_uboot.sh @@ -7,7 +7,7 @@ set -e # 6: invalid config main() { - local utag='v2023.07.02' + local utag='v2023.10' local atf_file='../rkbin/rk3568_bl31_v1.28.elf' local tpl_file='../rkbin/rk3568_ddr_1560MHz_v1.15.bin' @@ -87,137 +87,45 @@ main() { } cherry_pick() { - # regulator: implement basic reference counter - # https://github.com/u-boot/u-boot/commit/4fcba5d556b4224ad65a249801e4c9594d1054e8 - git -C u-boot cherry-pick 4fcba5d556b4224ad65a249801e4c9594d1054e8 + # pci: pcie_dw_rockchip: Configure number of lanes and link width speed + # https://github.com/u-boot/u-boot/commit/9af0c7732bf1df29138bb63712dc3fcbc6d821af + git -C u-boot cherry-pick 9af0c7732bf1df29138bb63712dc3fcbc6d821af - # regulator: rename dev_pdata to plat - # https://github.com/u-boot/u-boot/commit/29fca9f23a3b730cbf91c18617e25d9d8e3a26b7 - git -C u-boot cherry-pick 29fca9f23a3b730cbf91c18617e25d9d8e3a26b7 + # phy: rockchip: snps-pcie3: Refactor to use clk_bulk API + # https://github.com/u-boot/u-boot/commit/3b39592e8e245fc5c7b0a003ac65672ce9cfaf0f + git -C u-boot cherry-pick 3b39592e8e245fc5c7b0a003ac65672ce9cfaf0f - # dm: core: of_access: fix return value in of_property_match_string - # https://github.com/u-boot/u-boot/commit/15a2865515fdd77d1edbc10e275b7b5a4914aa79 - git -C u-boot cherry-pick 15a2865515fdd77d1edbc10e275b7b5a4914aa79 + # phy: rockchip: snps-pcie3: Refactor to use a phy_init ops + # https://github.com/u-boot/u-boot/commit/6cacdf842db5e62e9c26d015eddadd2f2410a6de + git -C u-boot cherry-pick 6cacdf842db5e62e9c26d015eddadd2f2410a6de - # rockchip: rk3568: Add support for FriendlyARM NanoPi R5S - # https://github.com/u-boot/u-boot/commit/0ef326b5e92ee7c0f3cd27385510eb5c211b10fb - git -C u-boot cherry-pick 0ef326b5e92ee7c0f3cd27385510eb5c211b10fb + # phy: rockchip: snps-pcie3: Add bifurcation support for RK3568 + # https://github.com/u-boot/u-boot/commit/1ebebfcc25bc8963cbdc6e35504160e5b745cabd + git -C u-boot cherry-pick 1ebebfcc25bc8963cbdc6e35504160e5b745cabd - # rockchip: rk3568: Add support for FriendlyARM NanoPi R5C - # https://github.com/u-boot/u-boot/commit/6a73211d4bb12d62ce82b33cee7d75d215a3d452 - git -C u-boot cherry-pick 6a73211d4bb12d62ce82b33cee7d75d215a3d452 + # phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588 + # https://github.com/u-boot/u-boot/commit/b37260bca1aa562c6c99527d997c768a12da017b + git -C u-boot cherry-pick b37260bca1aa562c6c99527d997c768a12da017b - # rockchip: rk3568: Fix alloc space exhausted in SPL - # https://github.com/u-boot/u-boot/commit/52472504e9c48cc1b34e0942c0075cd111ea85f0 - git -C u-boot cherry-pick 52472504e9c48cc1b34e0942c0075cd111ea85f0 + # rockchip: rk3568-nanopi-r5: Update defconfig for NanoPi R5C and R5S + # https://github.com/u-boot/u-boot/commit/5b155997d445f770e9a2c0d4a20e4eb13eedfede + git -C u-boot cherry-pick 5b155997d445f770e9a2c0d4a20e4eb13eedfede - # core: read: add dev_read_addr_size_index_ptr function - # https://github.com/u-boot/u-boot/commit/5e030632d49367944879e17a6d73828be22edd55 - git -C u-boot cherry-pick 5e030632d49367944879e17a6d73828be22edd55 + # rockchip: rk3568-nanopi-r5: Enable PCIe on NanoPi R5C and R5S + # https://github.com/u-boot/u-boot/commit/a9e9445ea2bb010444621e563a79bc33fe064f9c + git -C u-boot cherry-pick a9e9445ea2bb010444621e563a79bc33fe064f9c - # pci: pcie_dw_rockchip: Get config region from reg prop - # https://github.com/u-boot/u-boot/commit/bed7b2f00b1346f712f849d53c72fa8642601115 - git -C u-boot cherry-pick bed7b2f00b1346f712f849d53c72fa8642601115 + # power: regulator: Only run autoset once for each regulator + # https://github.com/u-boot/u-boot/commit/d99fb64a98af3bebf6b0c134291c4fb89e177aa2 + git -C u-boot cherry-pick d99fb64a98af3bebf6b0c134291c4fb89e177aa2 - # pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed - # https://github.com/u-boot/u-boot/commit/8b001ee59a9d4a6246098c8bc5bb894a752e7c0b - git -C u-boot cherry-pick 8b001ee59a9d4a6246098c8bc5bb894a752e7c0b + # regulator: rk8xx: Return correct voltage for buck converters + # https://github.com/u-boot/u-boot/commit/04c38c6c4936f353de36be60655f402922292a37 + git -C u-boot cherry-pick 04c38c6c4936f353de36be60655f402922292a37 - # pci: pcie_dw_rockchip: Speed up link probe - # https://github.com/u-boot/u-boot/commit/7ce186ada2ce1ece344dacc20244fb91866e435b - git -C u-boot cherry-pick 7ce186ada2ce1ece344dacc20244fb91866e435b - - # pci: pcie_dw_rockchip: Disable unused BARs of the root complex - # https://github.com/u-boot/u-boot/commit/bc6b94b5788677c3633e0331203578ffa706ff4b - git -C u-boot cherry-pick bc6b94b5788677c3633e0331203578ffa706ff4b - - # regulator: fixed: Add support for gpios prop - # https://github.com/u-boot/u-boot/commit/f7b8a84a29833b6e6ddac67920d688330b299fa8 - git -C u-boot cherry-pick f7b8a84a29833b6e6ddac67920d688330b299fa8 - - # rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support - # https://github.com/u-boot/u-boot/commit/583a82d5e2702f2c8aadcd75d416d6e45dd5188a - git -C u-boot cherry-pick 583a82d5e2702f2c8aadcd75d416d6e45dd5188a - - # rockchip: rk3568-rock-3a: Enable PCIe and NVMe support - # https://github.com/u-boot/u-boot/commit/a76aa6ffa6cd25eed282147f6e31b9c09272f930 - git -C u-boot cherry-pick a76aa6ffa6cd25eed282147f6e31b9c09272f930 - - # rockchip: rk356x: Update PCIe config, IO and memory regions - # https://github.com/u-boot/u-boot/commit/062b712999869bdd7d6283ab8eed50e5999ac88a - git -C u-boot cherry-pick 062b712999869bdd7d6283ab8eed50e5999ac88a - - # ata: dwc_ahci: Fix support for other platforms - # https://github.com/u-boot/u-boot/commit/7af6616c961d213b4bf2cc88003cbd868ea11ffa - git -C u-boot cherry-pick 7af6616c961d213b4bf2cc88003cbd868ea11ffa - - # cmd: ini: Fix build warning - # https://github.com/u-boot/u-boot/commit/8c1bb04b5699ce74ad727d4513e1a40a58c9c628 - git -C u-boot cherry-pick 8c1bb04b5699ce74ad727d4513e1a40a58c9c628 - - # board: rockchip: Add Hardkernel ODROID-M1 - # https://github.com/u-boot/u-boot/commit/94da929b933668c4b9ece7d56a2a2bb5543198c9 - git -C u-boot cherry-pick 94da929b933668c4b9ece7d56a2a2bb5543198c9 - - # Revert "arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb" - # https://github.com/u-boot/u-boot/commit/bec51f3fb316b5a5ccedd7deb2e58ae6d7443cfa - git -C u-boot cherry-pick bec51f3fb316b5a5ccedd7deb2e58ae6d7443cfa - - # usb: dwc3-generic: Return early when there is no child node - # https://github.com/u-boot/u-boot/commit/4412a2bf0b674d7438821531a0a19bbcd4b80eda - git -C u-boot cherry-pick 4412a2bf0b674d7438821531a0a19bbcd4b80eda - - # usb: dwc3-generic: Relax unsupported dr_mode check - # https://github.com/u-boot/u-boot/commit/6913c30516022f86104c9fbe315499e43eee4ed6 - git -C u-boot cherry-pick 6913c30516022f86104c9fbe315499e43eee4ed6 - - # usb: dwc3-generic: Add rk3568 support - # https://github.com/u-boot/u-boot/commit/caaeac88466f4152bd126e2342765a4b740955ae - git -C u-boot cherry-pick caaeac88466f4152bd126e2342765a4b740955ae - - # rockchip: rk3568: Use dwc3-generic driver - # https://github.com/u-boot/u-boot/commit/f8a2d1c108da37fd5202d717c3e428e3dfc12f01 - git -C u-boot cherry-pick f8a2d1c108da37fd5202d717c3e428e3dfc12f01 - - # rockchip: rk356x: Sync dtsi from linux v6.4 - # https://github.com/u-boot/u-boot/commit/0e3480c1f72f18f80690f8012404eacb67a61151 - git -C u-boot cherry-pick 0e3480c1f72f18f80690f8012404eacb67a61151 - - # rockchip: rk356x-u-boot: Add bootph-all to common pinctrl nodes - # https://github.com/u-boot/u-boot/commit/a3ef37a08df3c6aa463ad794e1f788d8a24b129c - git -C u-boot cherry-pick a3ef37a08df3c6aa463ad794e1f788d8a24b129c - - # rockchip: rk356x-u-boot: Use relaxed u-boot,spl-boot-order - # https://github.com/u-boot/u-boot/commit/f40dcc7d1e74ff5aa5f709918e26cb31277dcea0 - git -C u-boot cherry-pick f40dcc7d1e74ff5aa5f709918e26cb31277dcea0 - - # rockchip: rk3568-rock-3a: Fix SPI Flash alias - # https://github.com/u-boot/u-boot/commit/52f6b96d27c8aabca697ac395e86a3481f1c53b7 - git -C u-boot cherry-pick 52f6b96d27c8aabca697ac395e86a3481f1c53b7 - - # power: regulator: rk8xx: Add 500us delay after LDO regulator is enabled - # https://github.com/u-boot/u-boot/commit/fea7a29cc8d86a0bbcb4bcf740d47924839b1f81 - git -C u-boot cherry-pick fea7a29cc8d86a0bbcb4bcf740d47924839b1f81 - - # bootflow: Export setup_fs() - # https://github.com/u-boot/u-boot/commit/0c0c82b5177e9afb3a248da4d004f3dc48975c91 - git -C u-boot cherry-pick 0c0c82b5177e9afb3a248da4d004f3dc48975c91 - - # bootstd: Use a function to detect network in EFI bootmeth - # https://github.com/u-boot/u-boot/commit/146242cc998ed6e002831d4ff409189353e1960a - git -C u-boot cherry-pick 146242cc998ed6e002831d4ff409189353e1960a - - # bootstd: Avoid allocating memory for the EFI file - # https://github.com/u-boot/u-boot/commit/6a8c2f9781cede2a7cb2b95ee6310cd53b1c20e2 - git -C u-boot cherry-pick 6a8c2f9781cede2a7cb2b95ee6310cd53b1c20e2 - - # bootstd: Init the size before reading the devicetree - # https://github.com/u-boot/u-boot/commit/2984d21a28f812c9c1fd2243cc72796f69a61585 - git -C u-boot cherry-pick 2984d21a28f812c9c1fd2243cc72796f69a61585 - - # bootstd: Init the size before reading extlinux file - # https://github.com/u-boot/u-boot/commit/11158aef8939bb6e54361e4dae3809a9cbe78cff - git -C u-boot cherry-pick 11158aef8939bb6e54361e4dae3809a9cbe78cff + # regulator: rk8xx: Return correct voltage for switchout converters + # https://github.com/u-boot/u-boot/commit/bb657ffdd688dc08073734a402914ec0a8492d53 + git -C u-boot cherry-pick bb657ffdd688dc08073734a402914ec0a8492d53 } cp_to_debian() { diff --git a/uboot/patches/0001-ignore-build-artifacts.patch b/uboot/patches/0001-ignore-build-artifacts.patch index bca4387..8d8bb8a 100644 --- a/uboot/patches/0001-ignore-build-artifacts.patch +++ b/uboot/patches/0001-ignore-build-artifacts.patch @@ -1,15 +1,15 @@ -From c79b03d7448b370fe2eb6a9c5fb67bc9505de728 Mon Sep 17 00:00:00 2001 +From 1ab1a698b18bb0da8ba71612db6497f418a55ce1 Mon Sep 17 00:00:00 2001 From: John Clark Date: Tue, 7 Mar 2023 01:47:26 +0000 -Subject: [PATCH 1/9] ignore build artifacts +Subject: [PATCH] ignore build artifacts Signed-off-by: John Clark --- - .gitignore | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) + .gitignore | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore -index 3a4d056edf..27b515736b 100644 +index 002f95de4f..47f06f14c7 100644 --- a/.gitignore +++ b/.gitignore @@ -35,7 +35,7 @@ @@ -21,14 +21,26 @@ index 3a4d056edf..27b515736b 100644 # # Top-level generic files -@@ -44,6 +44,7 @@ fit-dtb.blob* +@@ -44,6 +44,9 @@ fit-dtb.blob* /MLO* /SPL* /System.map ++/mkimage-in-simple-bin* +/simple-bin* ++/tools/generated /u-boot* /boards.cfg /*.log +@@ -65,7 +68,8 @@ fit-dtb.blob* + # + # Generated include files + # +-/include/config/ ++include/autoconf.mk* ++/include/config* + /include/generated/ + + # stgit generated dirs -- -2.40.1 +2.42.0 diff --git a/uboot/patches/0002-fixup-rockchip-rk3568-Add-support-for-FriendlyARM-Na.patch b/uboot/patches/0002-fixup-rockchip-rk3568-Add-support-for-FriendlyARM-Na.patch deleted file mode 100644 index 7653bbe..0000000 --- a/uboot/patches/0002-fixup-rockchip-rk3568-Add-support-for-FriendlyARM-Na.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 9536c4290d8772d061d293d6bf35964dffc13ce4 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 3 Jul 2023 19:38:26 +0000 -Subject: [PATCH 2/9] fixup: rockchip: rk3568: Add support for FriendlyARM - NanoPi R5C - ---- - arch/arm/dts/rk3568-nanopi-r5c.dts | 2 +- - configs/nanopi-r5c-rk3568_defconfig | 18 ++++++++++++------ - 2 files changed, 13 insertions(+), 7 deletions(-) - -diff --git a/arch/arm/dts/rk3568-nanopi-r5c.dts b/arch/arm/dts/rk3568-nanopi-r5c.dts -index f70ca9f047..c718b8dbb9 100644 ---- a/arch/arm/dts/rk3568-nanopi-r5c.dts -+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts -@@ -106,7 +106,7 @@ - - rockchip-key { - reset_button_pin: reset-button-pin { -- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - }; -diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig -index 201b21ad77..833cff0e45 100644 ---- a/configs/nanopi-r5c-rk3568_defconfig -+++ b/configs/nanopi-r5c-rk3568_defconfig -@@ -1,5 +1,6 @@ - CONFIG_ARM=y - CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y - CONFIG_COUNTER_FREQUENCY=24000000 - CONFIG_ARCH_ROCKCHIP=y - CONFIG_TEXT_BASE=0x00a00000 -@@ -17,10 +18,13 @@ CONFIG_SPL_STACK=0x400000 - CONFIG_DEBUG_UART_BASE=0xFE660000 - CONFIG_DEBUG_UART_CLOCK=24000000 - CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_PCI=y - CONFIG_DEBUG_UART=y - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_FIT_SIGNATURE=y - CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" - # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_DISPLAY_BOARDINFO_LATE=y -@@ -37,14 +41,16 @@ CONFIG_CMD_GPIO=y - CONFIG_CMD_GPT=y - CONFIG_CMD_I2C=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y - CONFIG_CMD_USB=y - CONFIG_CMD_PMIC=y - CONFIG_CMD_REGULATOR=y - # CONFIG_SPL_DOS_PARTITION is not set - CONFIG_SPL_OF_CONTROL=y - CONFIG_OF_LIVE=y --CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" - CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_DM_SEQ_ALIAS=y - CONFIG_SPL_REGMAP=y - CONFIG_SPL_SYSCON=y - CONFIG_SPL_CLK=y -@@ -52,19 +58,20 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MISC=y - CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y --CONFIG_ETH_DESIGNWARE=y --CONFIG_GMAC_ROCKCHIP=y -+CONFIG_RTL8169=y -+CONFIG_PCIE_DW_ROCKCHIP=y - CONFIG_PHY_ROCKCHIP_INNO_USB2=y - CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y --CONFIG_POWER_DOMAIN=y -+CONFIG_SPL_PINCTRL=y - CONFIG_DM_PMIC=y - CONFIG_PMIC_RK8XX=y --CONFIG_SPL_DM_REGULATOR_FIXED=y - CONFIG_REGULATOR_RK8XX=y - CONFIG_PWM_ROCKCHIP=y - CONFIG_SPL_RAM=y -@@ -72,7 +79,6 @@ CONFIG_BAUDRATE=1500000 - CONFIG_DEBUG_UART_SHIFT=2 - CONFIG_SYS_NS16550_MEM32=y - CONFIG_SYSRESET=y --CONFIG_SYSRESET_PSCI=y - CONFIG_USB=y - CONFIG_USB_XHCI_HCD=y - CONFIG_USB_EHCI_HCD=y --- -2.40.1 - diff --git a/uboot/patches/0003-fixup-rockchip-rk3568-Add-support-for-FriendlyARM-Na.patch b/uboot/patches/0003-fixup-rockchip-rk3568-Add-support-for-FriendlyARM-Na.patch deleted file mode 100644 index e741c35..0000000 --- a/uboot/patches/0003-fixup-rockchip-rk3568-Add-support-for-FriendlyARM-Na.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 9bbb5bc3c0320371a87aeeb1ddc5f6a3a249a264 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 3 Jul 2023 20:39:52 +0000 -Subject: [PATCH 3/9] fixup: rockchip: rk3568: Add support for FriendlyARM - NanoPi R5S - ---- - arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 1 - - configs/nanopi-r5s-rk3568_defconfig | 19 +++++++++++++------ - 2 files changed, 13 insertions(+), 7 deletions(-) - -diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -index 0ecca85b20..b170db40c8 100644 ---- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -@@ -11,7 +11,6 @@ - / { - chosen { - stdout-path = &uart2; -- u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; - }; - }; - -diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig -index 67b2843070..c278ce083d 100644 ---- a/configs/nanopi-r5s-rk3568_defconfig -+++ b/configs/nanopi-r5s-rk3568_defconfig -@@ -1,5 +1,6 @@ - CONFIG_ARM=y - CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y - CONFIG_COUNTER_FREQUENCY=24000000 - CONFIG_ARCH_ROCKCHIP=y - CONFIG_TEXT_BASE=0x00a00000 -@@ -17,10 +18,13 @@ CONFIG_SPL_STACK=0x400000 - CONFIG_DEBUG_UART_BASE=0xFE660000 - CONFIG_DEBUG_UART_CLOCK=24000000 - CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_PCI=y - CONFIG_DEBUG_UART=y - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_FIT_SIGNATURE=y - CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" - # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_DISPLAY_BOARDINFO_LATE=y -@@ -37,14 +41,16 @@ CONFIG_CMD_GPIO=y - CONFIG_CMD_GPT=y - CONFIG_CMD_I2C=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y - CONFIG_CMD_USB=y - CONFIG_CMD_PMIC=y - CONFIG_CMD_REGULATOR=y - # CONFIG_SPL_DOS_PARTITION is not set - CONFIG_SPL_OF_CONTROL=y - CONFIG_OF_LIVE=y --CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" - CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_DM_SEQ_ALIAS=y - CONFIG_SPL_REGMAP=y - CONFIG_SPL_SYSCON=y - CONFIG_SPL_CLK=y -@@ -52,19 +58,21 @@ CONFIG_ROCKCHIP_GPIO=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MISC=y - CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y - CONFIG_MMC_DW=y - CONFIG_MMC_DW_ROCKCHIP=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_SDMA=y - CONFIG_MMC_SDHCI_ROCKCHIP=y --CONFIG_ETH_DESIGNWARE=y --CONFIG_GMAC_ROCKCHIP=y -+CONFIG_RTL8169=y -+CONFIG_NVME_PCI=y -+CONFIG_PCIE_DW_ROCKCHIP=y - CONFIG_PHY_ROCKCHIP_INNO_USB2=y - CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y --CONFIG_POWER_DOMAIN=y -+CONFIG_SPL_PINCTRL=y - CONFIG_DM_PMIC=y - CONFIG_PMIC_RK8XX=y --CONFIG_SPL_DM_REGULATOR_FIXED=y - CONFIG_REGULATOR_RK8XX=y - CONFIG_PWM_ROCKCHIP=y - CONFIG_SPL_RAM=y -@@ -72,7 +80,6 @@ CONFIG_BAUDRATE=1500000 - CONFIG_DEBUG_UART_SHIFT=2 - CONFIG_SYS_NS16550_MEM32=y - CONFIG_SYSRESET=y --CONFIG_SYSRESET_PSCI=y - CONFIG_USB=y - CONFIG_USB_XHCI_HCD=y - CONFIG_USB_EHCI_HCD=y --- -2.40.1 - diff --git a/uboot/patches/0004-pci-pcie_dw_rockchip-Configure-number-of-lanes-and-l.patch b/uboot/patches/0004-pci-pcie_dw_rockchip-Configure-number-of-lanes-and-l.patch deleted file mode 100644 index 6ba2ca1..0000000 --- a/uboot/patches/0004-pci-pcie_dw_rockchip-Configure-number-of-lanes-and-l.patch +++ /dev/null @@ -1,147 +0,0 @@ -From 9bc4d2fcc70864cb557d173bbe9d1ad49a4903b9 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 1 Aug 2023 11:46:54 +0000 -Subject: [PATCH 4/9] pci: pcie_dw_rockchip: Configure number of lanes and link - width speed - -Set number of lanes and link width speed control register based on the -num-lanes property. - -Code imported almost 1:1 from dw_pcie_setup in mainline linux. - -Signed-off-by: Jonas Karlman ---- - drivers/pci/pcie_dw_rockchip.c | 58 +++++++++++++++++++++++++++++----- - 1 file changed, 50 insertions(+), 8 deletions(-) - -diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c -index 1a35fae5c3..bc4635f671 100644 ---- a/drivers/pci/pcie_dw_rockchip.c -+++ b/drivers/pci/pcie_dw_rockchip.c -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -43,6 +44,7 @@ struct rk_pcie { - struct reset_ctl_bulk rsts; - struct gpio_desc rst_gpio; - u32 gen; -+ u32 num_lanes; - }; - - /* Parameters for the waiting for iATU enabled routine */ -@@ -152,12 +154,13 @@ static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, - * rk_pcie_configure() - Configure link capabilities and speed - * - * @rk_pcie: Pointer to the PCI controller state -- * @cap_speed: The capabilities and speed to configure - * - * Configure the link capabilities and speed in the PCIe root complex. - */ --static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) -+static void rk_pcie_configure(struct rk_pcie *pci) - { -+ u32 val; -+ - dw_pcie_dbi_write_enable(&pci->dw, true); - - /* Disable BAR 0 and BAR 1 */ -@@ -167,11 +170,49 @@ static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) - PCI_BASE_ADDRESS_1); - - clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY, -- TARGET_LINK_SPEED_MASK, cap_speed); -+ TARGET_LINK_SPEED_MASK, pci->gen); - - clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2, -- TARGET_LINK_SPEED_MASK, cap_speed); -+ TARGET_LINK_SPEED_MASK, pci->gen); -+ -+ /* Set the number of lanes */ -+ val = readl(pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL); -+ val &= ~PORT_LINK_FAST_LINK_MODE; -+ val |= PORT_LINK_DLL_LINK_EN; -+ val &= ~PORT_LINK_MODE_MASK; -+ switch (pci->num_lanes) { -+ case 1: -+ val |= PORT_LINK_MODE_1_LANES; -+ break; -+ case 2: -+ val |= PORT_LINK_MODE_2_LANES; -+ break; -+ case 4: -+ val |= PORT_LINK_MODE_4_LANES; -+ break; -+ default: -+ dev_err(pci->dw.dev, "num-lanes %u: invalid value\n", pci->num_lanes); -+ goto out; -+ } -+ writel(val, pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL); -+ -+ /* Set link width speed control register */ -+ val = readl(pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); -+ val &= ~PORT_LOGIC_LINK_WIDTH_MASK; -+ switch (pci->num_lanes) { -+ case 1: -+ val |= PORT_LOGIC_LINK_WIDTH_1_LANES; -+ break; -+ case 2: -+ val |= PORT_LOGIC_LINK_WIDTH_2_LANES; -+ break; -+ case 4: -+ val |= PORT_LOGIC_LINK_WIDTH_4_LANES; -+ break; -+ } -+ writel(val, pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); - -+out: - dw_pcie_dbi_write_enable(&pci->dw, false); - } - -@@ -231,11 +272,10 @@ static int is_link_up(struct rk_pcie *priv) - * rk_pcie_link_up() - Wait for the link to come up - * - * @rk_pcie: Pointer to the PCI controller state -- * @cap_speed: Desired link speed - * - * Return: 1 (true) for active line and negetive (false) for no link (timeout) - */ --static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) -+static int rk_pcie_link_up(struct rk_pcie *priv) - { - int retries; - -@@ -245,7 +285,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) - } - - /* DW pre link configurations */ -- rk_pcie_configure(priv, cap_speed); -+ rk_pcie_configure(priv); - - rk_pcie_disable_ltssm(priv); - rk_pcie_link_status_clear(priv); -@@ -341,7 +381,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) - rk_pcie_writel_apb(priv, 0x0, 0xf00040); - pcie_dw_setup_host(&priv->dw); - -- ret = rk_pcie_link_up(priv, priv->gen); -+ ret = rk_pcie_link_up(priv); - if (ret < 0) - goto err_link_up; - -@@ -419,6 +459,8 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) - priv->gen = dev_read_u32_default(dev, "max-link-speed", - LINK_SPEED_GEN_3); - -+ priv->num_lanes = dev_read_u32_default(dev, "num-lanes", 1); -+ - return 0; - - rockchip_pcie_parse_dt_err_phy_get_by_index: --- -2.40.1 - diff --git a/uboot/patches/0005-phy-rockchip-snps-pcie3-Refactor-to-use-clk_bulk-API.patch b/uboot/patches/0005-phy-rockchip-snps-pcie3-Refactor-to-use-clk_bulk-API.patch deleted file mode 100644 index ee2ac1e..0000000 --- a/uboot/patches/0005-phy-rockchip-snps-pcie3-Refactor-to-use-clk_bulk-API.patch +++ /dev/null @@ -1,133 +0,0 @@ -From 4ee980b5168346ce1a66147f771d652003928bfa Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 1 Aug 2023 11:46:54 +0000 -Subject: [PATCH 5/9] phy: rockchip: snps-pcie3: Refactor to use clk_bulk API - -Change to use clk_bulk API and syscon_regmap_lookup_by_phandle to -simplify in preparation for upcoming support of a RK3588 variant. - -Signed-off-by: Jonas Karlman ---- - .../phy/rockchip/phy-rockchip-snps-pcie3.c | 58 +++---------------- - 1 file changed, 9 insertions(+), 49 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -index 66c75f98e6..3053543a33 100644 ---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -26,17 +26,13 @@ - * @mmio: The base address of PHY internal registers - * @phy_grf: The regmap for controlling pipe signal - * @p30phy: The reset signal for PHY -- * @ref_clk_m: The reference clock of M for PHY -- * @ref_clk_n: The reference clock of N for PHY -- * @pclk: The clock for accessing PHY blocks -+ * @clks: The clocks for PHY - */ - struct rockchip_p3phy_priv { - void __iomem *mmio; - struct regmap *phy_grf; - struct reset_ctl p30phy; -- struct clk ref_clk_m; -- struct clk ref_clk_n; -- struct clk pclk; -+ struct clk_bulk clks; - }; - - static int rochchip_p3phy_init(struct phy *phy) -@@ -44,18 +40,10 @@ static int rochchip_p3phy_init(struct phy *phy) - struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); - int ret; - -- ret = clk_enable(&priv->ref_clk_m); -- if (ret < 0 && ret != -ENOSYS) -+ ret = clk_enable_bulk(&priv->clks); -+ if (ret) - return ret; - -- ret = clk_enable(&priv->ref_clk_n); -- if (ret < 0 && ret != -ENOSYS) -- goto err_ref; -- -- ret = clk_enable(&priv->pclk); -- if (ret < 0 && ret != -ENOSYS) -- goto err_pclk; -- - reset_assert(&priv->p30phy); - udelay(1); - -@@ -67,21 +55,13 @@ static int rochchip_p3phy_init(struct phy *phy) - udelay(1); - - return 0; --err_pclk: -- clk_disable(&priv->ref_clk_n); --err_ref: -- clk_disable(&priv->ref_clk_m); -- -- return ret; - } - - static int rochchip_p3phy_exit(struct phy *phy) - { - struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); - -- clk_disable(&priv->ref_clk_m); -- clk_disable(&priv->ref_clk_n); -- clk_disable(&priv->pclk); -+ clk_disable_bulk(&priv->clks); - reset_assert(&priv->p30phy); - - return 0; -@@ -90,21 +70,13 @@ static int rochchip_p3phy_exit(struct phy *phy) - static int rockchip_p3phy_probe(struct udevice *dev) - { - struct rockchip_p3phy_priv *priv = dev_get_priv(dev); -- struct udevice *syscon; - int ret; - - priv->mmio = dev_read_addr_ptr(dev); - if (!priv->mmio) - return -EINVAL; - -- ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, -- "rockchip,phy-grf", &syscon); -- if (ret) { -- pr_err("unable to find syscon device for rockchip,phy-grf\n"); -- return ret; -- } -- -- priv->phy_grf = syscon_get_regmap(syscon); -+ priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,phy-grf"); - if (IS_ERR(priv->phy_grf)) { - dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); - return PTR_ERR(priv->phy_grf); -@@ -116,22 +88,10 @@ static int rockchip_p3phy_probe(struct udevice *dev) - return ret; - } - -- ret = clk_get_by_name(dev, "refclk_m", &priv->ref_clk_m); -+ ret = clk_get_bulk(dev, &priv->clks); - if (ret) { -- dev_err(dev, "failed to find ref clock M\n"); -- return PTR_ERR(&priv->ref_clk_m); -- } -- -- ret = clk_get_by_name(dev, "refclk_n", &priv->ref_clk_n); -- if (ret) { -- dev_err(dev, "failed to find ref clock N\n"); -- return PTR_ERR(&priv->ref_clk_n); -- } -- -- ret = clk_get_by_name(dev, "pclk", &priv->pclk); -- if (ret) { -- dev_err(dev, "failed to find pclk\n"); -- return PTR_ERR(&priv->pclk); -+ dev_err(dev, "failed to get clocks\n"); -+ return ret; - } - - return 0; --- -2.40.1 - diff --git a/uboot/patches/0006-phy-rockchip-snps-pcie3-Refactor-to-use-a-phy_init-o.patch b/uboot/patches/0006-phy-rockchip-snps-pcie3-Refactor-to-use-a-phy_init-o.patch deleted file mode 100644 index d86dad9..0000000 --- a/uboot/patches/0006-phy-rockchip-snps-pcie3-Refactor-to-use-a-phy_init-o.patch +++ /dev/null @@ -1,84 +0,0 @@ -From e1a5b98b09c3b088eaefbc8d6edfda2d16818f8d Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 1 Aug 2023 11:46:55 +0000 -Subject: [PATCH 6/9] phy: rockchip: snps-pcie3: Refactor to use a phy_init ops - -Add a phy_init ops in preparation for upcoming support of a RK3588 -variant in the driver. - -Signed-off-by: Jonas Karlman ---- - .../phy/rockchip/phy-rockchip-snps-pcie3.c | 40 +++++++++++++++---- - 1 file changed, 32 insertions(+), 8 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -index 3053543a33..b76b5386be 100644 ---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -35,8 +35,32 @@ struct rockchip_p3phy_priv { - struct clk_bulk clks; - }; - -+struct rockchip_p3phy_ops { -+ int (*phy_init)(struct phy *phy); -+}; -+ -+static int rockchip_p3phy_rk3568_init(struct phy *phy) -+{ -+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); -+ -+ /* Deassert PCIe PMA output clamp mode */ -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, -+ (0x1 << 15) | (0x1 << 31)); -+ -+ reset_deassert(&priv->p30phy); -+ udelay(1); -+ -+ return 0; -+} -+ -+static const struct rockchip_p3phy_ops rk3568_ops = { -+ .phy_init = rockchip_p3phy_rk3568_init, -+}; -+ - static int rochchip_p3phy_init(struct phy *phy) - { -+ struct rockchip_p3phy_ops *ops = -+ (struct rockchip_p3phy_ops *)dev_get_driver_data(phy->dev); - struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); - int ret; - -@@ -47,14 +71,11 @@ static int rochchip_p3phy_init(struct phy *phy) - reset_assert(&priv->p30phy); - udelay(1); - -- /* Deassert PCIe PMA output clamp mode */ -- regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, -- (0x1 << 15) | (0x1 << 31)); -- -- reset_deassert(&priv->p30phy); -- udelay(1); -+ ret = ops->phy_init(phy); -+ if (ret) -+ clk_disable_bulk(&priv->clks); - -- return 0; -+ return ret; - } - - static int rochchip_p3phy_exit(struct phy *phy) -@@ -103,7 +124,10 @@ static struct phy_ops rochchip_p3phy_ops = { - }; - - static const struct udevice_id rockchip_p3phy_of_match[] = { -- { .compatible = "rockchip,rk3568-pcie3-phy" }, -+ { -+ .compatible = "rockchip,rk3568-pcie3-phy", -+ .data = (ulong)&rk3568_ops, -+ }, - { }, - }; - --- -2.40.1 - diff --git a/uboot/patches/0007-phy-rockchip-snps-pcie3-Add-bifurcation-support-for-.patch b/uboot/patches/0007-phy-rockchip-snps-pcie3-Add-bifurcation-support-for-.patch deleted file mode 100644 index 0575c04..0000000 --- a/uboot/patches/0007-phy-rockchip-snps-pcie3-Add-bifurcation-support-for-.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 7680dec61b44d7ca1ae34a93a3be5d199b144585 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 1 Aug 2023 11:46:54 +0000 -Subject: [PATCH 7/9] phy: rockchip: snps-pcie3: Add bifurcation support for - RK3568 - -Configure aggregation or bifurcation mode on RK3568 based on the value -of data-lanes property. - -Code imported almost 1:1 from mainline linux driver. - -Fixes: 6ec62b6ca698 ("phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY") -Signed-off-by: Jonas Karlman ---- - .../phy/rockchip/phy-rockchip-snps-pcie3.c | 65 +++++++++++++++++-- - 1 file changed, 59 insertions(+), 6 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -index b76b5386be..642819b1f6 100644 ---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -16,9 +16,16 @@ - #include - #include - --#define GRF_PCIE30PHY_CON1 0x4 --#define GRF_PCIE30PHY_CON6 0x18 --#define GRF_PCIE30PHY_CON9 0x24 -+/* Register for RK3568 */ -+#define GRF_PCIE30PHY_CON1 0x4 -+#define GRF_PCIE30PHY_CON6 0x18 -+#define GRF_PCIE30PHY_CON9 0x24 -+#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31)) -+#define GRF_PCIE30PHY_STATUS0 0x80 -+#define GRF_PCIE30PHY_WR_EN (0xf << 16) -+#define SRAM_INIT_DONE(reg) (reg & BIT(14)) -+ -+#define RK3568_BIFURCATION_LANE_0_1 BIT(0) - - /** - * struct rockchip_p3phy_priv - RK DW PCIe PHY state -@@ -27,12 +34,16 @@ - * @phy_grf: The regmap for controlling pipe signal - * @p30phy: The reset signal for PHY - * @clks: The clocks for PHY -+ * @num_lanes: The number of lane to controller mappings -+ * @lanes: The lane to controller mapping - */ - struct rockchip_p3phy_priv { - void __iomem *mmio; - struct regmap *phy_grf; - struct reset_ctl p30phy; - struct clk_bulk clks; -+ int num_lanes; -+ u32 lanes[4]; - }; - - struct rockchip_p3phy_ops { -@@ -42,15 +53,40 @@ struct rockchip_p3phy_ops { - static int rockchip_p3phy_rk3568_init(struct phy *phy) - { - struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev); -+ bool bifurcation = false; -+ int ret; -+ u32 reg; - - /* Deassert PCIe PMA output clamp mode */ -- regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, -- (0x1 << 15) | (0x1 << 31)); -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM); -+ -+ for (int i = 0; i < priv->num_lanes; i++) { -+ if (priv->lanes[i] > 1) -+ bifurcation = true; -+ } -+ -+ /* Set bifurcation if needed, and it doesn't care RC/EP */ -+ if (bifurcation) { -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, -+ GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1); -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, -+ GRF_PCIE30PHY_DA_OCM); -+ } else { -+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, -+ GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1); -+ } - - reset_deassert(&priv->p30phy); - udelay(1); - -- return 0; -+ ret = regmap_read_poll_timeout(priv->phy_grf, -+ GRF_PCIE30PHY_STATUS0, -+ reg, SRAM_INIT_DONE(reg), -+ 0, 500); -+ if (ret) -+ dev_err(phy->dev, "lock failed 0x%x\n", reg); -+ -+ return ret; - } - - static const struct rockchip_p3phy_ops rk3568_ops = { -@@ -103,6 +139,23 @@ static int rockchip_p3phy_probe(struct udevice *dev) - return PTR_ERR(priv->phy_grf); - } - -+ ret = dev_read_size(dev, "data-lanes"); -+ if (ret > 0) { -+ priv->num_lanes = ret / sizeof(u32); -+ if (priv->num_lanes < 2 || -+ priv->num_lanes > ARRAY_SIZE(priv->lanes)) { -+ dev_err(dev, "unsupported data-lanes property size\n"); -+ return -EINVAL; -+ } -+ -+ ret = dev_read_u32_array(dev, "data-lanes", priv->lanes, -+ priv->num_lanes); -+ if (ret) { -+ dev_err(dev, "failed to read data-lanes property\n"); -+ return ret; -+ } -+ } -+ - ret = reset_get_by_name(dev, "phy", &priv->p30phy); - if (ret) { - dev_err(dev, "no phy reset control specified\n"); --- -2.40.1 - diff --git a/uboot/patches/0008-phy-rockchip-naneng-combphy-Use-signal-from-comb-PHY.patch b/uboot/patches/0008-phy-rockchip-naneng-combphy-Use-signal-from-comb-PHY.patch deleted file mode 100644 index 2869edb..0000000 --- a/uboot/patches/0008-phy-rockchip-naneng-combphy-Use-signal-from-comb-PHY.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 848306a30bf5d5a39b9536e750d5fd30a3886ce5 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Wed, 2 Aug 2023 09:23:59 +0000 -Subject: [PATCH 8/9] phy: rockchip: naneng-combphy: Use signal from comb PHY - on RK3588 - -Route signal from comb PHY instead of PCIe3 PHY to PCIe1l0 and PCIe1l1. - -Fixes use of pcie2x1l0 on ROCK 5B. - -Code imported from mainline linux driver. - -Fixes: c5b4a012bca8 ("phy: rockchip: naneng-combphy: Support rk3588") -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -index d5408ccac9..9ca66bf8db 100644 ---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -@@ -61,6 +61,8 @@ struct rockchip_combphy_grfcfg { - struct combphy_reg pipe_con1_for_sata; - struct combphy_reg pipe_sgmii_mac_sel; - struct combphy_reg pipe_xpcs_phy_ready; -+ struct combphy_reg pipe_pcie1l0_sel; -+ struct combphy_reg pipe_pcie1l1_sel; - struct combphy_reg u3otg0_port_en; - struct combphy_reg u3otg1_port_en; - }; -@@ -435,6 +437,8 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) - param_write(priv->phy_grf, &cfg->con1_for_pcie, true); - param_write(priv->phy_grf, &cfg->con2_for_pcie, true); - param_write(priv->phy_grf, &cfg->con3_for_pcie, true); -+ param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); -+ param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); - break; - case PHY_TYPE_USB3: - param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); -@@ -507,6 +511,8 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { - /* pipe-grf */ - .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, - .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, -+ .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 }, -+ .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 }, - }; - - static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { --- -2.40.1 - diff --git a/uboot/patches/0009-rockchip-rk3568-nanopi-r5-Enable-PCIe-on-NanoPi-R5C-.patch b/uboot/patches/0009-rockchip-rk3568-nanopi-r5-Enable-PCIe-on-NanoPi-R5C-.patch deleted file mode 100644 index d6325b8..0000000 --- a/uboot/patches/0009-rockchip-rk3568-nanopi-r5-Enable-PCIe-on-NanoPi-R5C-.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 883821b313c3234fbc507e5a5fb560e971315ff9 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 1 Aug 2023 11:46:55 +0000 -Subject: [PATCH 9/9] rockchip: rk3568-nanopi-r5: Enable PCIe on NanoPi R5C and - R5S - -Enable missing PCIe Kconfig options now that PCIe bifurcation is fixed -to make use of the two on-board RTL8125B and the M.2 slot on NanoPi R5C -and NanoPi R5S. - -Signed-off-by: Jonas Karlman ---- - arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 4 ++++ - arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 4 ++++ - 2 files changed, 8 insertions(+) - -diff --git a/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi -index fe5bc6af47..c0798e950b 100644 ---- a/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi -+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi -@@ -1,3 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-or-later OR MIT - - #include "rk3568-nanopi-r5s-u-boot.dtsi" -+ -+&pcie3x2 { -+ /delete-property/ vpcie3v3-supply; -+}; -diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -index b170db40c8..5ee9905694 100644 ---- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -@@ -14,6 +14,10 @@ - }; - }; - -+&pcie3x1 { -+ /delete-property/ vpcie3v3-supply; -+}; -+ - &sdhci { - cap-mmc-highspeed; - mmc-ddr-1_8v; --- -2.40.1 -