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Using assert fmt with reset fails on functions #1879

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grebe opened this issue Jan 23, 2025 · 0 comments
Open

Using assert fmt with reset fails on functions #1879

grebe opened this issue Jan 23, 2025 · 0 comments
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codegen Related to emitting (System)Verilog.

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@grebe
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grebe commented Jan 23, 2025

Describe the bug
Using an assert fmt string can fail when codegening something that doesn't generate registers. Even if you specify a reset, the current behavior means it won't be populated unless there's a user. The way op overrides add an assert format string means that it won't look like a reset user at block conversion. You end up with an error like: Assert format string has {rst} placeholder, but block has no reset signal..

To Reproduce
Steps to reproduce the behavior:

  1. Make a function with an assertion that will codegen with no registers (e.g. set pipeline_stages=1)
  2. Run codegen with an assert format string that uses {rst}.
  3. See error

Expected behavior
This should codegen properly with a reset port that gets sent to the assert fmt string.

@grebe grebe added the codegen Related to emitting (System)Verilog. label Jan 23, 2025
@grebe grebe self-assigned this Jan 23, 2025
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Labels
codegen Related to emitting (System)Verilog.
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