From f52c723f7a17a38cafa6157699e4fe588229e8a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Radim=20Karni=C5=A1?= Date: Thu, 3 Oct 2024 17:56:23 +0200 Subject: [PATCH] docs: Add ESP32-C5 and ESP32-C61 docs --- .gitlab-ci.yml | 4 +- docs/_static/esptool_versions.js | 2 + docs/conf_common.py | 4 + .../advanced-topics/boot-mode-selection.rst | 6 +- .../advanced-topics/firmware-image-format.rst | 20 +- docs/en/espefuse/inc/summary_ESP32-C5.rst | 198 ++++++++++++++++++ docs/en/espefuse/inc/summary_ESP32-C61.rst | 161 ++++++++++++++ docs/en/esptool/advanced-options.rst | 2 +- docs/en/esptool/flash-modes.rst | 4 +- docs/requirements.txt | 2 +- 10 files changed, 393 insertions(+), 10 deletions(-) create mode 100644 docs/en/espefuse/inc/summary_ESP32-C5.rst create mode 100644 docs/en/espefuse/inc/summary_ESP32-C61.rst diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d2f3db90c2..89c5ab46b0 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -433,7 +433,7 @@ target_esp32c61: tags: - esptool_esp32c61_target script: - - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32C61 --chip esp32c61 --baud 115200 + - coverage run --parallel-mode -m pytest ${CI_PROJECT_DIR}/test/test_esptool.py --port /dev/serial_ports/ESP32C61 --chip esp32c61 --baud 115200 .windows_test: stage: test @@ -523,7 +523,7 @@ build_docs: script: - cd docs - pip install -r requirements.txt --prefer-binary - - build-docs -l en -t {esp8266,esp32,esp32s2,esp32c3,esp32s3,esp32c2,esp32c6,esp32h2,esp32p4} + - build-docs -l en -t {esp8266,esp32,esp32s2,esp32c3,esp32s3,esp32c2,esp32c6,esp32h2,esp32p4,esp32c5,esp32c61} .deploy_docs_template: stage: deploy_docs diff --git a/docs/_static/esptool_versions.js b/docs/_static/esptool_versions.js index 409ecf2e9b..6414ff4fd1 100644 --- a/docs/_static/esptool_versions.js +++ b/docs/_static/esptool_versions.js @@ -13,5 +13,7 @@ var DOCUMENTATION_VERSIONS = { { text: "ESP32-C6", value: "esp32c6" }, { text: "ESP32-H2", value: "esp32h2" }, { text: "ESP32-P4", value: "esp32p4" }, + { text: "ESP32-C5", value: "esp32c5" }, + { text: "ESP32-C61", value: "esp32c61" }, ] }; diff --git a/docs/conf_common.py b/docs/conf_common.py index 03e69fc861..dc44c047c1 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -11,6 +11,8 @@ "esp32c6", "esp32h2", "esp32p4", + "esp32c5", + "esp32c61", ] # link roles config @@ -42,6 +44,8 @@ "esp32c6": ESP32_DOCS, "esp32h2": ESP32_DOCS, "esp32p4": ESP32_DOCS, + "esp32c5": ESP32_DOCS, + "esp32c61": ESP32_DOCS, } # Extra options required by sphinx_idf_theme diff --git a/docs/en/advanced-topics/boot-mode-selection.rst b/docs/en/advanced-topics/boot-mode-selection.rst index dfa4a04e37..31597f102c 100644 --- a/docs/en/advanced-topics/boot-mode-selection.rst +++ b/docs/en/advanced-topics/boot-mode-selection.rst @@ -1,6 +1,6 @@ -{IDF_TARGET_STRAP_BOOT_GPIO:default="GPIO9", esp32="GPIO0", esp32s2="GPIO0", esp32s3="GPIO0", esp32p4="GPIO35"} +{IDF_TARGET_STRAP_BOOT_GPIO:default="GPIO9", esp32="GPIO0", esp32s2="GPIO0", esp32s3="GPIO0", esp32p4="GPIO35", esp32c5="GPIO28"} -{IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO8", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46", esp32p4="GPIO36"} +{IDF_TARGET_STRAP_BOOT_2_GPIO:default="GPIO8", esp32="GPIO2", esp32s2="GPIO46", esp32s3="GPIO46", esp32p4="GPIO36", esp32c5="GPIO27"} {IDF_TARGET_BOOTLOADER_OFFSET:default="0", esp32="1000", esp32s2="1000", esp32p4="2000"} @@ -87,7 +87,7 @@ This guide explains how to select the boot mode correctly and describes the boot {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be either left unconnected/floating, or driven Low, in order to enter the serial bootloader. - .. only:: esp32c3 or esp32c2 or esp32h2 or esp32c6 or esp32p4 + .. only:: esp32c3 or esp32c2 or esp32h2 or esp32c6 or esp32p4 or esp32c5 or esp32c61 {IDF_TARGET_STRAP_BOOT_2_GPIO} must also be driven High, in order to enter the serial bootloader reliably. The strapping combination of {IDF_TARGET_STRAP_BOOT_2_GPIO} = 0 and {IDF_TARGET_STRAP_BOOT_GPIO} = 0 is invalid and will trigger unexpected behavior. diff --git a/docs/en/advanced-topics/firmware-image-format.rst b/docs/en/advanced-topics/firmware-image-format.rst index 10d81bb576..92f7a52439 100644 --- a/docs/en/advanced-topics/firmware-image-format.rst +++ b/docs/en/advanced-topics/firmware-image-format.rst @@ -91,7 +91,25 @@ The image header is 8 bytes long: Flash frequency with value ``0`` can mean either 80MHz or 40MHz based on MSPI clock source mode. -.. only:: not (esp8266 or esp32c6 or esp32s3 or esp32s2 or esp32p4) +.. only:: esp32c5 or esp32c61 + + +--------+------------------------------------------------------------------------------------------------+ + | Byte | Description | + +========+================================================================================================+ + | 0 | Magic number (always ``0xE9``) | + +--------+------------------------------------------------------------------------------------------------+ + | 1 | Number of segments | + +--------+------------------------------------------------------------------------------------------------+ + | 2 | SPI Flash Mode (``0`` = QIO, ``1`` = QOUT, ``2`` = DIO, ``3`` = DOUT) | + +--------+------------------------------------------------------------------------------------------------+ + | 3 | High four bits - Flash size (``0`` = 1MB, ``1`` = 2MB, ``2`` = 4MB, ``3`` = 8MB, ``4`` = 16MB) | + | | | + | | Low four bits - Flash frequency (``0xf`` = {IDF_TARGET_FLASH_FREQ_F}MHz, ``0`` = {IDF_TARGET_FLASH_FREQ_0}MHz, ``2`` = {IDF_TARGET_FLASH_FREQ_2}MHz) | + +--------+------------------------------------------------------------------------------------------------+ + | 4-7 | Entry point address | + +--------+------------------------------------------------------------------------------------------------+ + +.. only:: not (esp8266 or esp32c6 or esp32s3 or esp32s2 or esp32p4 or esp32c5 or esp32c61) +--------+------------------------------------------------------------------------------------------------+ | Byte | Description | diff --git a/docs/en/espefuse/inc/summary_ESP32-C5.rst b/docs/en/espefuse/inc/summary_ESP32-C5.rst new file mode 100644 index 0000000000..32e0a48c14 --- /dev/null +++ b/docs/en/espefuse/inc/summary_ESP32-C5.rst @@ -0,0 +1,198 @@ +.. code-block:: none + + > espefuse.py -p PORT summary + + Connecting.... + Detecting chip type... ESP32-C5 + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Config fuses: + WR_DIS (BLOCK0) Disable programming of individual eFuses = 4608 R/W (0x00001200) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled.\ = False R/W (0b0) + \ 1: disabled\\ 0: enabled\\ + DIS_TWAI (BLOCK0) Represents whether TWAI function is disabled or en = False R/W (0b0) + abled.\\ 1: disabled\\ 0: enabled\\ + KM_DISABLE_DEPLOY_MODE (BLOCK0) Represents whether the deploy mode of key manager = 0 R/W (0x0) + is disable or not. \\ 1: disabled \\ 0: enabled.\\ + KM_RND_SWITCH_CYCLE (BLOCK0) Set the bits to control key manager random number = 0 R/W (0b00) + switch cycle. 0: control by register. 1: 8 km clk + cycles. 2: 16 km cycles. 3: 32 km cycles + KM_DEPLOY_ONLY_ONCE (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0x0) + can only be deployed once. 1 is true; 0 is false. + bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds + DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) + enabled.\\ 1: disabled\\ 0: enabled\\ + UART_PRINT_CONTROL (BLOCK0) Set the default UARTboot message output mode = Enable R/W (0b00) + HYS_EN_PAD (BLOCK0) Represents whether the hysteresis function of corr = False R/W (0b0) + esponding PAD is enabled.\\ 1: enabled\\ 0:disable + d\\ + HUK_GEN_STATE (BLOCK0) Set the bits to control validation of HUK generate = 0 R/W (0b000000000) + mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid + .\\ + XTAL_48M_SEL (BLOCK0) Represents whether XTAL frequency is 48MHz or not. = 1 R/W (0b001) + If not; 40MHz XTAL will be used. If this field co + ntains Odd number bit 1: Enable 48MHz XTAL\ Even n + umber bit 1: Enable 40MHz XTAL + XTAL_48M_SEL_MODE (BLOCK0) Specify the XTAL frequency selection is decided by = True R/W (0b1) + eFuse or strapping-PAD-state. 1: eFuse\\ 0: strap + ping-PAD-state + ECC_FORCE_CONST_TIME (BLOCK0) Represents whether to force ecc to use const-time = False R/W (0b0) + calculation mode. \\ 1: Enable. \\ 0: Disable + PSRAM_CAP (BLOCK1) Psram capacity = 0 R/W (0b000) + PSRAM_VENDOR (BLOCK1) Psram vendor = 0 R/W (0b00) + TEMP (BLOCK1) Temp (die embedded inside) = 0 R/W (0b00) + TRIM_N_BIAS (BLOCK1) PADC CAL N bias = 0 R/W (0b00000) + TRIM_P_BIAS (BLOCK1) PADC CAL P bias = 0 R/W (0b00000) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) + in unit of ms. When the value less than 15; the wa + iting time is the programmed value. Otherwise; the + waiting time is 2 times the programmed value + FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) + sume command during SPI boot.\\ 1: forced\\ 0:not + forced\\ + FLASH_CAP (BLOCK1) Flash capacity = 0 R/W (0b000) + FLASH_VENDOR (BLOCK1) Flash vendor = 0 R/W (0b000) + + Identity fuses: + WAFER_VERSION_MINOR (BLOCK1) Minor chip version = 0 R/W (0x0) + WAFER_VERSION_MAJOR (BLOCK1) Minor chip version = 0 R/W (0b00) + DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK1) Disables check of blk version major = False R/W (0b0) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) + BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + PA_TRIM_VERSION (BLOCK1) PADC CAL PA trim version = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Jtag fuses: + JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio15 when b + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 is enabled or disabled.\\ 1: enabled\\ + 0: disabled\\ + SOFT_DIS_JTAG (BLOCK0) Represents whether JTAG is disabled in soft way.\\ = 0 R/W (0b000) + Odd number: disabled\\ Even number: enabled\\ + DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) + y(permanently).\\ 1: disabled\\ 0: enabled\\ + + Mac fuses: + MAC (BLOCK1) MAC address + = 60:55:f9:f9:54:1c (OK) R/W + MAC_EXT (BLOCK1) Represents the extended bits of MAC address = ff:fe (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W + MAC_EUI64 (BLOCK1) calc MAC_EUI64 = MAC[0]:MAC[1]:MAC[2]:MAC_EXT[0]:M + = 60:55:f9:ff:fe:f9:54:1c (OK) R/W + AC_EXT[1]:MAC[3]:MAC[4]:MAC[5] + + Security fuses: + DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) + nto download mode is disabled or enabled.\\ 1: dis + abled\\ 0: enabled\\ + SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0) + e_download is disabled or enabled.\\ 1: disabled\\ + 0: enabled\\ + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) + led or enabled(except in SPI boot mode).\\ 1: disa + bled\\ 0: enabled\\ + FORCE_USE_KEY_MANAGER_KEY (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0x0) + must come from key manager. 1 is true; 0 is false. + bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds + FORCE_DISABLE_SW_INIT_KEY (BLOCK0) Set this bit to disable software written init key; = False R/W (0b0) + and force use efuse_init_key + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/- (0x0) + KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/- (0x0) + KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) + SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) + clock random divide mode + SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led.\\ 1: enabled\\ 0: disabled\\ + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) + is enabled or disabled.\\ 1: enabled.\\ 0: disabl + ed\\ + KM_XTS_KEY_LENGTH_256 (BLOCK0) Set this bitto configure flash encryption use xts- = False R/W (0b0) + 128 key. else use xts-256 key + DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disabled or en = False R/W (0b0) + abled.\\ 1: disabled\\ 0: enabled\\ + LOCK_KM_KEY (BLOCK0) Represetns whether to lock the efuse xts key.\\ 1. = False R/W (0b0) + Lock\\ 0: Unlock\\ + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) + disabled.\\ 1: enabled\\ 0: disabled\\ + SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) + ck feature + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST VERIFY ON WAKE is disabled = False R/W (0b0) + or enabled when Secure Boot is enabled.\\ 1: disa + bled\\ 0: enabled\\ + XTS_DPA_PSEUDO_LEVEL (BLOCK0) Represents the pseudo round level of xts-aes anti- = 0 R/W (0b00) + dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: D + isabled\\ + XTS_DPA_CLK_ENABLE (BLOCK0) Represents whether xts-aes anti-dpa attack clock i = False R/W (0b0) + s enabled.\\ 1. Enable.\\ 0: Disable.\\ + ECDSA_DISABLE_P192 (BLOCK0) Represents whether to disable P192 curve in ECDSA. = False R/W (0b0) + \\ 1: Disabled.\\ 0: Not disable + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Usb fuses: + DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) + tag is disabled or enabled.\\ 1: disabled\\ 0: ena + bled\\ + USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0) + .\\ 1: exchanged\\ 0: not exchanged\\ + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0) + isabled or enabled.\\ 1: disabled\\ 0: enabled\\ + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) + nction is disabled or enabled.\\ 1: Disable\\ 0: E + nable\\ + + Vdd fuses: + VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as gp = False R/W (0b0) + io.\\ 1: functioned\\ 0: not functioned\\ + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) Represents the threshold level of the RTC watchdog = 0 R/W (0b00) + STG0 timeout.\\ 0: Original threshold configurati + on value of STG0 *2 \\1: Original threshold config + uration value of STG0 *4 \\2: Original threshold c + onfiguration value of STG0 *8 \\3: Original thresh + old configuration value of STG0 *16 \\ diff --git a/docs/en/espefuse/inc/summary_ESP32-C61.rst b/docs/en/espefuse/inc/summary_ESP32-C61.rst new file mode 100644 index 0000000000..7bdd7f7855 --- /dev/null +++ b/docs/en/espefuse/inc/summary_ESP32-C61.rst @@ -0,0 +1,161 @@ +.. code-block:: none + + > espefuse.py -p PORT summary + + Connecting.... + Detecting chip type... ESP32-C61 + + === Run "summary" command === + EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) + ---------------------------------------------------------------------------------------- + Config fuses: + WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) + RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) + DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enabled.\ = False R/W (0b0) + \ 1: disabled\\ 0: enabled\\ + DIS_DIRECT_BOOT (BLOCK0) Represents whether direct boot mode is disabled or = False R/W (0b0) + enabled.\\ 1. Disable\\ 0: Enable\\ + UART_PRINT_CONTROL (BLOCK0) Represents the types of UART printing = 0 R/W (0b00) + HYS_EN_PAD (BLOCK0) Represents whether the hysteresis function of corr = False R/W (0b0) + esponding PAD is enabled.\\ 1: enabled\\ 0:disable + d\\ + DIS_WIFI6 (BLOCK0) Represents whether the WiFi 6 feature is enable or = False R/W (0b0) + disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is en + abled.\\ + ECC_FORCE_CONST_TIME (BLOCK0) Represents whether to force ecc to use const-time = False R/W (0b0) + calculation mode. \\ 1: Enable. \\ 0: Disable + PSRAM_CAP (BLOCK1) PSRAM capacity = 1 R/W (0b001) + PSRAM_VENDOR (BLOCK1) PSRAM vendor = 1 R/W (0b01) + TEMP (BLOCK1) Temperature = 1 R/W (0b01) + BLOCK_USR_DATA (BLOCK3) User data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Flash fuses: + FLASH_TPUW (BLOCK0) Represents the flash waiting time after power-up; = 0 R/W (0x0) + in unit of ms. When the value less than 15; the wa + iting time is programmed value. Otherwise; the wai + ting time is 2 times the programmed value + FORCE_SEND_RESUME (BLOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0) + sume command during SPI boot + FLASH_CAP (BLOCK1) Flash capacity = 0 R/W (0b000) + FLASH_VENDOR (BLOCK1) Flash vendor = 0 R/W (0b000) + + Identity fuses: + WAFER_VERSION_MINOR (BLOCK1) Minor chip version = 1 R/W (0x1) + WAFER_VERSION_MAJOR (BLOCK1) Major chip version = 0 R/W (0b00) + DISABLE_WAFER_VERSION_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0) + DISABLE_BLK_VERSION_MAJOR (BLOCK1) Disables check of blk version major = False R/W (0b0) + BLK_VERSION_MINOR (BLOCK1) BLK_VERSION_MINOR of BLOCK2 = 0 R/W (0b000) + BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR of BLOCK2 = 0 R/W (0b00) + PKG_VERSION (BLOCK1) Package version = 0 R/W (0b000) + OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID + = 75 7f 2d 6e 1c 1c 60 c6 6a 63 e6 d0 d8 8a 5b 14 R/W + + Jtag fuses: + JTAG_SEL_ENABLE (BLOCK0) Represents whether the selection between usb_to_jt = False R/W (0b0) + ag and pad_to_jtag through strapping gpio15 when b + oth EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are + equal to 0 is enabled or disabled.\\ 1: enabled\\ + 0: disabled\\ + DIS_PAD_JTAG (BLOCK0) Represents whether JTAG is disabled in the hard wa = False R/W (0b0) + y(permanently).\\ 1: disabled\\ 0: enabled\\ + + Mac fuses: + MAC (BLOCK1) MAC address + = 60:55:f9:fb:17:58 (OK) R/W + CUSTOM_MAC (BLOCK3) Custom MAC + = 00:00:00:00:00:00 (OK) R/W + + Security fuses: + DIS_FORCE_DOWNLOAD (BLOCK0) Represents whether the function that forces chip i = False R/W (0b0) + nto download mode is disabled or enabled.\\ 1: dis + abled\\ 0: enabled\\ + SPI_DOWNLOAD_MSPI_DIS (BLOCK0) Represents whether SPI0 controller during boot_mod = False R/W (0b0) + e_download is disabled or enabled.\\ 1: disabled\\ + 0: enabled\\ + DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Represents whether flash encrypt function is disab = False R/W (0b0) + led or enabled(except in SPI boot mode).\\ 1: disa + bled\\ 0: enabled\\ + SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) + and disables otherwise + SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) + SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) + KEY_PURPOSE_0 (BLOCK0) Represents the purpose of Key0 = USER R/W (0x0) + KEY_PURPOSE_1 (BLOCK0) Represents the purpose of Key1 = USER R/W (0x0) + KEY_PURPOSE_2 (BLOCK0) Represents the purpose of Key2 = USER R/W (0x0) + KEY_PURPOSE_3 (BLOCK0) Represents the purpose of Key3 = USER R/W (0x0) + KEY_PURPOSE_4 (BLOCK0) Represents the purpose of Key4 = USER R/W (0x0) + KEY_PURPOSE_5 (BLOCK0) Represents the purpose of Key5 = USER R/W (0x0) + SEC_DPA_LEVEL (BLOCK0) Represents the spa secure level by configuring the = 0 R/W (0b00) + clock random divide mode + SECURE_BOOT_EN (BLOCK0) Represents whether secure boot is enabled or disab = False R/W (0b0) + led.\\ 1: enabled\\ 0: disabled\\ + SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Represents whether revoking aggressive secure boot = False R/W (0b0) + is enabled or disabled.\\ 1: enabled.\\ 0: disabl + ed\\ + DIS_DOWNLOAD_MODE (BLOCK0) Represents whether Download mode is disable or ena = False R/W (0b0) + ble.\\ 1. Disable\\ 0: Enable\\ + ENABLE_SECURITY_DOWNLOAD (BLOCK0) Represents whether security download is enabled or = False R/W (0b0) + disabled.\\ 1: Enable\\ 0: Disable\\ + SECURE_VERSION (BLOCK0) Represents the version used by ESP-IDF anti-rollba = 0 R/W (0x0000) + ck feature + SECURE_BOOT_DISABLE_FAST_WAKE (BLOCK0) Represents whether FAST_VERIFY_ON_WAKE is disable = False R/W (0b0) + or enable when Secure Boot is enable + XTS_DPA_CLK_ENABLE (BLOCK0) Represents whether anti-dpa attack clock function = False R/W (0b0) + is enabled.\\ 1. Enable\\ 0: Disable\\ + XTS_DPA_PSEUDO_LEVEL (BLOCK0) Represents the anti-dpa attack pseudo function lev = 0 R/W (0b00) + el.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided b + y register configuration\\ + ECDSA_DISABLE_P192 (BLOCK0) Represents whether to disable P192 curve in ECDSA. = False R/W (0b0) + \\ 1: Disabled.\\ 0: Not disable + BLOCK_KEY0 (BLOCK4) + Purpose: USER + Key0 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY1 (BLOCK5) + Purpose: USER + Key1 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY2 (BLOCK6) + Purpose: USER + Key2 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY3 (BLOCK7) + Purpose: USER + Key3 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY4 (BLOCK8) + Purpose: USER + Key4 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + BLOCK_KEY5 (BLOCK9) + Purpose: USER + Key5 or user data + = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W + + Usb fuses: + DIS_USB_JTAG (BLOCK0) Represents whether the function of usb switch to j = False R/W (0b0) + tag is disabled or enabled.\\ 1: disabled\\ 0: ena + bled\\ + USB_EXCHG_PINS (BLOCK0) Represents whether the D+ and D- pins is exchanged = False R/W (0b0) + .\\ 1: exchanged\\ 0: not exchanged\\ + DIS_USB_SERIAL_JTAG_ROM_PRINT (BLOCK0) Represents whether print from USB-Serial-JTAG is d = False R/W (0b0) + isabled or enabled.\\ 1. Disable\\ 0: Enable\\ + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BLOCK0) Represents whether the USB-Serial-JTAG download fu = False R/W (0b0) + nction is disabled or enabled.\\ 1: Disable\\ 0: E + nable\\ + + Vdd fuses: + VDD_SPI_AS_GPIO (BLOCK0) Represents whether vdd spi pin is functioned as gp = False R/W (0b0) + io.\\ 1: functioned\\ 0: not functioned\\ + + Wdt fuses: + WDT_DELAY_SEL (BLOCK0) Represents the threshold level of the RTC watchdog = 0 R/W (0b00) + STG0 timeout.\\ 0: Original threshold configurati + on value of STG0 *2 \\1: Original threshold config + uration value of STG0 *4 \\2: Original threshold c + onfiguration value of STG0 *8 \\3: Original thresh + old configuration value of STG0 *16 \\ diff --git a/docs/en/esptool/advanced-options.rst b/docs/en/esptool/advanced-options.rst index 53ede5cf2f..a5e00c7956 100644 --- a/docs/en/esptool/advanced-options.rst +++ b/docs/en/esptool/advanced-options.rst @@ -22,7 +22,7 @@ The ``--before`` argument allows you to specify whether the chip needs resetting * ``--before default_reset`` is the default, which uses DTR & RTS serial control lines (see :ref:`entering-the-bootloader`) to try to reset the chip into bootloader mode. * ``--before no_reset`` will skip DTR/RTS control signal assignments and just start sending a serial synchronisation command to the chip. This is useful if your chip doesn't have DTR/RTS, or for some serial interfaces (like Arduino board onboard serial) which behave differently when DTR/RTS are toggled. * ``--before no_reset_no_sync`` will skip DTR/RTS control signal assignments and skip also the serial synchronization command. This is useful if your chip is already running the :ref:`stub bootloader ` and you want to avoid resetting the chip and uploading the stub again. - :esp32c3 or esp32s3 or esp32c6 or esp32h2 or esp32p4: * ``--before usb_reset`` will use custom reset sequence for USB-JTAG-Serial (used for example for ESP chips connected through the USB-JTAG-Serial peripheral). Usually, this option doesn't have to be used directly. Esptool should be able to detect connection through USB-JTAG-Serial. + :esp32c3 or esp32s3 or esp32c6 or esp32h2 or esp32p4 or esp32c5 or esp32c61: * ``--before usb_reset`` will use custom reset sequence for USB-JTAG-Serial (used for example for ESP chips connected through the USB-JTAG-Serial peripheral). Usually, this option doesn't have to be used directly. Esptool should be able to detect connection through USB-JTAG-Serial. Reset After Operation ^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/esptool/flash-modes.rst b/docs/en/esptool/flash-modes.rst index b9d18686d0..9d5481ba8b 100644 --- a/docs/en/esptool/flash-modes.rst +++ b/docs/en/esptool/flash-modes.rst @@ -4,7 +4,7 @@ {IDF_TARGET_FLASH_FREQ_0:default="40", esp32c2="30", esp32h2="24"} -{IDF_TARGET_FLASH_FREQ:default="``40m``, ``26m``, ``20m``, ``80m``", esp32c2="``30m``, ``20m``, ``15m``, ``60m``", esp32h2="``24m``, ``16m``, ``12m``, ``48m``", esp32c6="``40m``, ``20m``, ``80m``"} +{IDF_TARGET_FLASH_FREQ:default="``40m``, ``26m``, ``20m``, ``80m``", esp32c2="``30m``, ``20m``, ``15m``, ``60m``", esp32h2="``24m``, ``16m``, ``12m``, ``48m``", esp32c6="``40m``, ``20m``, ``80m``, esp32c5="``40m``, ``20m``, ``80m``, esp32c61="``40m``, ``20m``, ``80m``"} .. _flash-modes: @@ -56,7 +56,7 @@ Size of the SPI flash, given in megabytes. Valid values are: ``keep``, ``detect``, ``256KB``, ``512KB``, ``1MB``, ``2MB``, ``4MB``, ``2MB-c1``, ``4MB-c1``, ``8MB``, ``16MB`` -.. only:: esp32 or esp32c3 or esp32c6 or esp32c2 or esp32h2 +.. only:: esp32 or esp32c3 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61 Valid values are: ``keep``, ``detect``, ``1MB``, ``2MB``, ``4MB``, ``8MB``, ``16MB`` diff --git a/docs/requirements.txt b/docs/requirements.txt index 948dda348e..51936f4f01 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1 +1 @@ -esp-docs~=1.5 +esp-docs~=1.10